Deprecations all over the place

.github/test_sets/get_test_matrix.py

@@ -40,10 +40,21 @@
 )
 @click.argument("test_sets", nargs=-1)
 def main(scls, use_json, test_sets):
-
     data_str = open(TEST_SETS_FILE).read()
     data = yaml.safe_load(data_str)
-    test_set_data = filter(lambda e: e["scl"] in scls and e["name"] in test_sets, data)
+
+    all_scls = set([e["scl"] for e in data])
+    selected_scls = set()
+    for pattern in scls:
+        if pattern.endswith("/"):
+            for scl in all_scls:
+                if scl.startswith(pattern):
+                    selected_scls.add(scl)
+        else:
+            selected_scls.add(pattern)
+    test_set_data = filter(
+        lambda e: e["scl"] in selected_scls and e["name"] in test_sets, data
+    )
 
     designs = list()
     for test_set in list(test_set_data):

Makefile

@@ -48,7 +48,7 @@ include ./dependencies/image_name.mk
 TEST_DESIGN ?= spm
 DESIGN_LIST ?= spm
 QUICK_RUN_DESIGN ?= spm
-BENCHMARK ?= regression_results/benchmark_results/SW_HD.csv
+BENCHMARK ?= regression_results/benchmark_results/sky130A/sky130_fd_sc_hd.csv
 REGRESSION_TAG ?= TEST_SW_HD
 FASTEST_TEST_SET_TAG ?= FASTEST_TEST_SET
 EXTENDED_TEST_SET_TAG ?= EXTENDED_TEST_SET
@@ -171,10 +171,10 @@ venv/created: ./requirements.txt ./requirements_dev.txt ./requirements_lint.txt
 
 DLTAG=custom_design_List
 .PHONY: test_design_list fastest_test_set extended_test_set
-fastest_test_set: DESIGN_LIST=$(shell python3 ./.github/test_sets/get_test_matrix.py --plain --pdk $(PDK) fastest_test_set)
+fastest_test_set: DESIGN_LIST=$(shell python3 ./.github/test_sets/get_test_matrix.py --plain --scl $(PDK)/$(STD_CELL_LIBRARY) fastest_test_set)
 fastest_test_set: DLTAG=$(FASTEST_TEST_SET_TAG)
 fastest_test_set: test_design_list
-extended_test_set: DESIGN_LIST=$(shell python3 ./.github/test_sets/get_test_matrix.py --plain --pdk $(PDK) extended_test_set)
+extended_test_set: DESIGN_LIST=$(shell python3 ./.github/test_sets/get_test_matrix.py --plain --scl $(PDK)/$(STD_CELL_LIBRARY) extended_test_set)
 extended_test_set: DLTAG=$(EXTENDED_TEST_SET_TAG)
 extended_test_set: test_design_list
 test_design_list:

configuration/checkers.tcl

@@ -17,10 +17,7 @@ set ::env(QUIT_ON_ASSIGN_STATEMENTS) 0
 set ::env(QUIT_ON_UNMAPPED_CELLS) 1
 set ::env(QUIT_ON_SYNTH_CHECKS) 1
 set ::env(SYNTH_CHECKS_ALLOW_TRISTATE) 1
-set ::env(LINTER_RELATIVE_INCLUDES) 1
 set ::env(LINTER_INCLUDE_PDK_MODELS) 1
-set ::env(QUIT_ON_LINTER_WARNINGS) 0
-set ::env(QUIT_ON_LINTER_ERRORS) 1
 
 # STA
 set ::env(QUIT_ON_TIMING_VIOLATIONS) 1

configuration/floorplan.tcl

@@ -12,8 +12,6 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
-set ::env(DESIGN_IS_CORE) 1
-
 # Floorplan defaults
 set ::env(FP_SIZING) relative
 set ::env(FP_CORE_UTIL) 50
@@ -45,8 +43,6 @@ set ::env(TOP_MARGIN_MULT) 4
 set ::env(LEFT_MARGIN_MULT) 12
 set ::env(RIGHT_MARGIN_MULT) 12
 
-set ::env(FP_PDN_HORIZONTAL_HALO) 10
-set ::env(FP_PDN_VERTICAL_HALO) $::env(FP_PDN_HORIZONTAL_HALO)
 set ::env(FP_TAP_HORIZONTAL_HALO) 10
 set ::env(FP_TAP_VERTICAL_HALO) $::env(FP_TAP_HORIZONTAL_HALO)
 set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) 1

configuration/general.tcl

@@ -15,7 +15,6 @@
 # General Defaults
 set ::env(CLOCK_PERIOD) "10.0"
 set ::env(USE_GPIO_PADS) 0
-set ::env(RSZ_DONT_TOUCH_RX) "$^"
 set ::env(RSZ_MULTICORNER_LIB) 1
 set ::env(RSZ_DONT_TOUCH) ""
 
@@ -41,7 +40,6 @@ set ::env(RUN_IRDROP_REPORT) 1
 
 ## Signoff
 set ::env(RUN_CVC) 1
-set ::env(PRIMARY_GDSII_STREAMOUT_TOOL) magic
 
 ### Netgen
 set ::env(RUN_LVS) 1

configuration/synthesis.tcl

@@ -28,7 +28,6 @@ set ::env(SYNTH_STRATEGY) "AREA 0"
 set ::env(SYNTH_ADDER_TYPE) "YOSYS"
 set ::env(CLOCK_BUFFER_FANOUT) 16
 set ::env(SYNTH_READ_BLACKBOX_LIB) 0
-set ::env(SYNTH_ELABORATE_ONLY) 0
 set ::env(SYNTH_FLAT_TOP) 0
 set ::env(IO_PCT) 0.2
 set ::env(SYNTH_EXTRA_MAPPING_FILE) ""

docs/source/reference/configuration.md

@@ -148,7 +148,7 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
 | `FP_TAP_VERTICAL_HALO` <a id="FP_TAP_VERTICAL_HALO"></a> | Specify the vertical halo size around macros during tap insertion. The value provided is in microns. <br> (Default: set to the value of `FP_TAP_HORIZONTAL_HALO`) |
 | `FP_PDN_HORIZONTAL_HALO` <a id="FP_PDN_HORIZONTAL_HALO"></a> | Sets the horizontal halo around the macros during power grid insertion. The value provided is in microns. <br> (Default: `10`) |
 | `FP_PDN_VERTICAL_HALO` <a id="FP_PDN_VERTICAL_HALO"></a> | Sets the vertical halo around the macros during power grid insertion. The value provided is in microns. <br> (Default: set to the value of `FP_PDN_HORIZONTAL_HALO`) |
-| `DESIGN_IS_CORE` <a id="DESIGN_IS_CORE"></a> | Controls the layers used in the power grid. Depending on whether the design is the core of the chip or a macro inside the core. 1=Is a Core, 0=Is a Macro <br> (Default: `1`)|
+| `FP_PDN_FULL_STACK` <a id="FP_PDN_FULL_STACK"></a> | Controls the layers used in the power grid. If set to `0` (Tcl)/`false` (JSON), only the lower, vertical layer will be used, which is useful when hardening a macro for integrating into a larger top-level design. <br> (Default: `1`)|
 | `FP_PIN_ORDER_CFG` <a id="FP_PIN_ORDER_CFG"></a> | Points to the pin order configuration file to set the pins in specific directions (S, W, E, N). If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. `$<number>` i.e. `$1` can be used to place a virtual pin where `<number>` is the count of virtual pins. This can create separation between pins. You can also use `@min_distance=<number>` i.e. `@min_distance=0.8` to set preferred min distance between pins in a specific direction. See spm configuration file as an example.<br> (Default: NONE)|
 | `FP_CONTEXT_DEF` <a id="FP_CONTEXT_DEF"></a> | Points to the parent DEF file that includes this macro/design and uses this DEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_LEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: NONE)|
 | `FP_CONTEXT_LEF` <a id="FP_CONTEXT_LEF"></a> | Points to the parent LEF file that includes this macro/design and uses this LEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_DEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: NONE)|
@@ -161,6 +161,7 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
 | `PDN_CFG` <a id="PDN_CFG"></a> | **Deprecated: Use `FP_PDN_CFG`**: Points to a PDN configuration file that describes how to construct the PDN in detail. |
 | `FP_HORIZONTAL_HALO` <a id="FP_HORIZONTAL_HALO"></a> | **Deprecated: Use `FP_PDN_HORIZONTAL_HALO`**: Sets the horizontal halo around the macros during power grid insertion. The value provided is in microns.|
 | `FP_PDN_VERTICAL_HALO` <a id="FP_PDN_VERTICAL_HALO"></a> | **Deprecated: Use `FP_PDN_VERTICAL_HALO`**: Sets the vertical halo around the macros during power grid insertion. The value provided is in microns. |
+| `DESIGN_IS_CORE` <a id="DESIGN_IS_CORE"></a> | **Deprecated as even macros can have a full-stack PDN if core rings are used: New variable is `FP_PDN_FULL_STACK`** Controls the layers used in the power grid. Depending on whether the design is the core of the chip or a macro inside the core. 1=Is a Core, 0=Is a Macro <br> (Default: `1`)|
 | `FP_PDN_IRDROP` <a id="FP_PDN_IRDROP"></a> | **Removed: No point running it this early in the flow**: Enable calculation of power grid IR drop during PDN generation. |
 
 ### Deprecated I/O Layer variables

docs/source/tutorials/digital_guide.md

@@ -58,7 +58,7 @@ Modify the `config.json` to include following:
 :language: json
 ```
 
-`DESIGN_IS_CORE` controls the metal levels used for power routing. Set it to `false` to use only lower levels.
+`FP_PDN_FULL_STACK` controls the metal levels used for power routing. Set it to `false` to use only lower levels.
 
 `FP_PDN_CORE_RING` is set to `false` to disable a power ring around the macroblock.
 
@@ -136,7 +136,7 @@ Then add `VERILOG_FILES_BLACKBOX`, `EXTRA_LEFS` and `EXTRA_GDS_FILES` to the `co
   "VERILOG_FILES": "dir::src/*.v",
   "CLOCK_PORT": "clk",
   "CLOCK_PERIOD": 10.0,
-  "DESIGN_IS_CORE": true,
+  "FP_PDN_FULL_STACK": true,
 
   "EXTRA_LEFS": "/openlane/designs/ci/mem_1r1w/runs/full_guide/results/final/lef/mem_1r1w.lef",
   "EXTRA_GDS_FILES": "/openlane/designs/ci/mem_1r1w/runs/full_guide/results/final/gds/mem_1r1w.gds",
@@ -156,7 +156,7 @@ This is a [known issue documented here](https://github.com/The-OpenROAD-Project/
 
 The PDN straps will be routed in opposite directions.
 In locations where the two routings cross each other,
-VIAs connecting the layers are added. When `DESIGN_IS_CORE` is set to `true` then higher layers (met5 in sky130) are used.
+VIAs connecting the layers are added. When `FP_PDN_FULL_STACK` is set to `true` then higher layers (met5 in sky130) are used.
 If it is set to `false` then VIAs will be missing and you will get LVS issues.
 
 ### Verilog files
@@ -493,15 +493,15 @@ Fanout     Cap    Slew   Delay    Time   Description
 
 ### Demo: Debugging LVS issues due to PDN issues
 
-Copy the original `regfile_2r1w` as `regfile_2r1w_design_not_core`. Change `DESIGN_IS_CORE` to `false`.
+Copy the original `regfile_2r1w` as `regfile_2r1w_design_not_core`. Change `FP_PDN_FULL_STACK` to `false`.
 
 ```
 {
     "DESIGN_NAME": "regfile_2r1w",
     "VERILOG_FILES": "dir::src/*.v",
     "CLOCK_PORT": "clk",
     "CLOCK_PERIOD": 10.0,
-    "DESIGN_IS_CORE": false,
+    "FP_PDN_FULL_STACK": false,
 
     "FP_ASPECT_RATIO": 2,
     "EXTRA_LEFS":      "/openlane/designs/ci/mem_1r1w/runs/full_guide/results/final/lef/mem_1r1w.lef",
@@ -589,7 +589,7 @@ The submacros are by default logically connected to `VPWR/VGND` power domain.
 As can be seen, the PDN is missing the power straps in layer `met5`.
 Therefore the layout, does not have connections to the submacro, while the net is logically connected.
 
-This is expected as it was disabled by setting `DESIGN_IS_CORE` to `false` above.
+This is expected as it was disabled by setting `FP_PDN_FULL_STACK` to `false` above.
 Of course, reverting the change fixes this issue.
 
 :::{note}

docs/source/usage/advanced_power_grid_control.md

@@ -31,7 +31,7 @@ The first decision to make at the core level is the core ring. So first, you nee
 <td>
 
 ```json
-    "DESIGN_IS_CORE": true,
+    "FP_PDN_FULL_STACK": true,
     "FP_PDN_CORE_RING": true,
     "VDD_NETS": "vccd1 vccd2 vdda1 cdda2",
     "GND_NETS": "vssd1 vssd2 vssa1 vssa2",
@@ -44,7 +44,7 @@ The first decision to make at the core level is the core ring. So first, you nee
 <td>
 
 ```tcl
-set ::env(DESIGN_IS_CORE) 1
+set ::env(FP_PDN_FULL_STACK) 1
 set ::env(FP_PDN_CORE_RING) 1
 set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
 set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
@@ -198,7 +198,7 @@ To begin the configurations for your macro, you want to announce that the design
 <td>
 
 ```json
-    "DESIGN_IS_CORE": false,
+    "FP_PDN_FULL_STACK": false,
     "FP_PDN_CORE_RING": false,
     "RT_MAX_LAYER": "met4"
 ```
@@ -208,7 +208,7 @@ To begin the configurations for your macro, you want to announce that the design
 <td>
 
 ```tcl
-set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_FULL_STACK) 0
 set ::env(FP_PDN_CORE_RING) 0
 set ::env(RT_MAX_LAYER) "met4"
 ```

docs/source/usage/chip_integration.md

@@ -99,7 +99,7 @@ It should have an `stdcell` section that includes a `core_ring` on met4 and met5
 <td>
 
 ```json
-    "DESIGN_IS_CORE": true,
+    "FP_PDN_FULL_STACK": true,
     "FP_PDN_CORE_RING": true
 ```
 
@@ -108,7 +108,7 @@ It should have an `stdcell` section that includes a `core_ring` on met4 and met5
 <td>
 
 ```tcl
-    set ::env(DESIGN_IS_CORE) 1
+    set ::env(FP_PDN_FULL_STACK) 1
     set ::env(FP_PDN_CORE_RING) 1
 ```
 </td>

docs/source/usage/hardening_macros.md

@@ -21,7 +21,7 @@ Click on any variable name listed in this document to get its usage information.
 * [`VERILOG_FILES`](../reference/configuration.md#VERILOG_FILES)
 * [`CLOCK_PORT`](../reference/configuration.md#CLOCK_PORT)
 * [`CLOCK_PERIOD`](../reference/configuration.md#CLOCK_PERIOD)
-* [`DESIGN_IS_CORE`](../reference/configuration.md#DESIGN_IS_CORE) (You may leave it empty if true)
+* [`FP_PDN_FULL_STACK`](../reference/configuration.md#FP_PDN_FULL_STACK) (You may leave it empty if true)
 
 So, for example:
 
@@ -44,7 +44,7 @@ set ::env(DESIGN_NAME) {spm}
 
 set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
 set ::env(CLOCK_PORT) {clk}
-set ::env(DESIGN_IS_CORE) {0}
+set ::env(FP_PDN_FULL_STACK) {0}
 ```
 
 </td>

scripts/config/init.py

@@ -72,7 +72,7 @@ def init_config(
                         set ::env(CLOCK_PORT) "clk"
                         set ::env(CLOCK_PERIOD) "10.0"
 
-                        set ::env(DESIGN_IS_CORE) {{1}}
+                        set ::env(FP_PDN_FULL_STACK) {{1}}
 
                         set tech_specific_config "$::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl"
                         if {{ [file exists $tech_specific_config] == 1 }} {{
@@ -93,7 +93,7 @@ def init_config(
                         "VERILOG_FILES": verilog_arg,
                         "CLOCK_PORT": "clk",
                         "CLOCK_PERIOD": 10.0,
-                        "DESIGN_IS_CORE": True,
+                        "FP_PDN_FULL_STACK": True,
                     },
                     indent=4,
                     sort_keys=False,

scripts/openroad/common/pdn_cfg.tcl

@@ -43,52 +43,49 @@ foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
 set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
     -secondary_power $secondary
 
-# Assesses whether the design is the core of the chip or not based on the
-# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
-if { $::env(DESIGN_IS_CORE) == 1 } {
-    # Used if the design is the core of the chip
-    define_pdn_grid \
-        -name stdcell_grid \
-        -starts_with POWER \
-        -voltage_domain CORE \
-        -pins "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
+set pdn_grid_common_args [list]
+lappend pdn_grid_common_args -starts_with POWER
+if { $::env(FP_PDN_CORE_RING) } {
+    lappend pdn_grid_common_args -extend_to_core_ring
+}
 
-    add_pdn_stripe \
-        -grid stdcell_grid \
-        -layer $::env(FP_PDN_VERTICAL_LAYER) \
-        -width $::env(FP_PDN_VWIDTH) \
-        -pitch $::env(FP_PDN_VPITCH) \
-        -offset $::env(FP_PDN_VOFFSET) \
-        -spacing $::env(FP_PDN_VSPACING) \
-        -starts_with POWER -extend_to_core_ring
+set used_layer_list "$::env(FP_PDN_VERTICAL_LAYER)"
+
+if { $::env(FP_PDN_FULL_STACK) == 1 } {
+    set used_layer_list "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
+}
+
+define_pdn_grid \
+    -name stdcell_grid \
+    -starts_with POWER \
+    -voltage_domain CORE \
+    -pins "$used_layer_list"
 
+
+add_pdn_stripe \
+    -grid stdcell_grid \
+    -layer $::env(FP_PDN_VERTICAL_LAYER) \
+    -width $::env(FP_PDN_VWIDTH) \
+    -pitch $::env(FP_PDN_VPITCH) \
+    -offset $::env(FP_PDN_VOFFSET) \
+    -spacing $::env(FP_PDN_VSPACING) \
+    {*}$pdn_grid_common_args
+
+if { $::env(FP_PDN_FULL_STACK) == 1 } {
     add_pdn_stripe \
         -grid stdcell_grid \
         -layer $::env(FP_PDN_HORIZONTAL_LAYER) \
         -width $::env(FP_PDN_HWIDTH) \
         -pitch $::env(FP_PDN_HPITCH) \
         -offset $::env(FP_PDN_HOFFSET) \
         -spacing $::env(FP_PDN_HSPACING) \
-        -starts_with POWER -extend_to_core_ring
+        {*}$pdn_grid_common_args
+}
 
+if { [llength $used_layer_list] >= 2 } {
     add_pdn_connect \
         -grid stdcell_grid \
-        -layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
-} else {
-    # Used if the design is a macro in the core
-    define_pdn_grid \
-        -name stdcell_grid \
-        -starts_with POWER \
-        -voltage_domain CORE \
-        -pins $::env(FP_PDN_VERTICAL_LAYER)
-
-    add_pdn_stripe \
-        -grid stdcell_grid \
-        -layer $::env(FP_PDN_VERTICAL_LAYER) \
-        -width $::env(FP_PDN_VWIDTH) \
-        -pitch $::env(FP_PDN_VPITCH) \
-        -offset $::env(FP_PDN_VOFFSET) \
-        -starts_with POWER
+        -layers "$used_layer_list"
 }
 
 # Adds the standard cell rails if enabled.
@@ -125,4 +122,4 @@ define_pdn_grid \
 
 add_pdn_connect \
     -grid macro \
-    -layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
+    -layers "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"

scripts/openroad/pdn.tcl

@@ -16,6 +16,10 @@ source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
 read
 
 # load the grid definitions
+
+## For backwards compat
+set ::env(DESIGN_IS_CORE) $::env(FP_PDN_FULL_STACK)
+
 if {[catch {source $::env(FP_PDN_CFG)} errmsg]} {
     puts stderr $errmsg
     exit 1