Check if CLOCK_PORT is found in the design

Remove misleading CTS log print

scripts/openroad/cts.tcl

@@ -37,7 +37,6 @@ if { [info exists ::env(MAX_TRANSITION_CONSTRAINT)] } {
 configure_cts_characterization {*}$cts_characterization_args
 
 puts "\[INFO]: Performing clock tree synthesis..."
-puts "\[INFO]: Looking for the following net(s): $::env(CLOCK_NET)"
 puts "\[INFO]: Running Clock Tree Synthesis..."
 
 set arg_list [list]

scripts/openroad/sta/check_clock_port.tcl

@@ -0,0 +1,24 @@
+# Copyright 2023 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
+
+read_libs -typical $::env(LIB_TYPICAL)
+read_netlist
+
+if { [get_ports $::env(CLOCK_PORT)] == "" } {
+    puts "\[ERROR]: CLOCK_PORT: '$::env(CLOCK_PORT)' not part of the design"
+    exit 1
+} else {
+    puts "\[INFO]: CLOCK_PORT: '$::env(CLOCK_PORT)' found"
+}

scripts/tcl_commands/synthesis.tcl

@@ -75,6 +75,9 @@ proc run_yosys {args} {
         exec rm -f $arg_values(-output).bak
     }
     unset ::env(SAVE_NETLIST)
+    set log [index_file $::env(synthesis_logs)/check_clock_port.log]
+    puts_info "Checking clock port (log: [relpath . $log])"
+    run_sta_script $::env(SCRIPTS_DIR)/openroad/sta/check_clock_port.tcl -indexed_log $log
 }
 
 proc run_synth_exploration {args} {