Ameliorate Warnings, PDN Generation, and the default design (#2066)

~ Reimplemented the default serial/parallel multiplier to be a bit less cryptic and eliminate linter warnings; and added a proper testbench
~ Reimplemented deprecated variable translation behavior to account for the situation where a deprecated variable's value does not match the default for the new value, which causes a crash
~ Slightly improved warning for designs having been black-boxed during STA
~ PDN Generation Updates
    ~ Renamed `DESIGN_IS_CORE` to `FP_PDN_MULTILAYER` with translation behavior
    ~ PDN generation will now always attempt to extend to core ring (which is inert if core rings do not exist)
    ~ Fixed bug where `FP_PDN_MULTILAYER` being set to `0` would attempt to create a core-ring on two layers anyway
~ IR drop now prints a warning if `VSRC_LOC_FILE` is not provided
- Removed deprecation behavior for `GLB_RT` variables - it's been over a year (>=6 mo as promised)

.github/test_sets/get_test_matrix.py

@@ -40,10 +40,21 @@
 )
 @click.argument("test_sets", nargs=-1)
 def main(scls, use_json, test_sets):
-
     data_str = open(TEST_SETS_FILE).read()
     data = yaml.safe_load(data_str)
-    test_set_data = filter(lambda e: e["scl"] in scls and e["name"] in test_sets, data)
+
+    all_scls = set([e["scl"] for e in data])
+    selected_scls = set()
+    for pattern in scls:
+        if pattern.endswith("/"):
+            for scl in all_scls:
+                if scl.startswith(pattern):
+                    selected_scls.add(scl)
+        else:
+            selected_scls.add(pattern)
+    test_set_data = filter(
+        lambda e: e["scl"] in selected_scls and e["name"] in test_sets, data
+    )
 
     designs = list()
     for test_set in list(test_set_data):

Makefile

@@ -48,7 +48,7 @@ include ./dependencies/image_name.mk
 TEST_DESIGN ?= spm
 DESIGN_LIST ?= spm
 QUICK_RUN_DESIGN ?= spm
-BENCHMARK ?= regression_results/benchmark_results/SW_HD.csv
+BENCHMARK ?= regression_results/benchmark_results/sky130A/sky130_fd_sc_hd.csv
 REGRESSION_TAG ?= TEST_SW_HD
 FASTEST_TEST_SET_TAG ?= FASTEST_TEST_SET
 EXTENDED_TEST_SET_TAG ?= EXTENDED_TEST_SET
@@ -171,10 +171,10 @@ venv/created: ./requirements.txt ./requirements_dev.txt ./requirements_lint.txt
 
 DLTAG=custom_design_List
 .PHONY: test_design_list fastest_test_set extended_test_set
-fastest_test_set: DESIGN_LIST=$(shell python3 ./.github/test_sets/get_test_matrix.py --plain --pdk $(PDK) fastest_test_set)
+fastest_test_set: DESIGN_LIST=$(shell python3 ./.github/test_sets/get_test_matrix.py --plain --scl $(PDK)/$(STD_CELL_LIBRARY) fastest_test_set)
 fastest_test_set: DLTAG=$(FASTEST_TEST_SET_TAG)
 fastest_test_set: test_design_list
-extended_test_set: DESIGN_LIST=$(shell python3 ./.github/test_sets/get_test_matrix.py --plain --pdk $(PDK) extended_test_set)
+extended_test_set: DESIGN_LIST=$(shell python3 ./.github/test_sets/get_test_matrix.py --plain --scl $(PDK)/$(STD_CELL_LIBRARY) extended_test_set)
 extended_test_set: DLTAG=$(EXTENDED_TEST_SET_TAG)
 extended_test_set: test_design_list
 test_design_list:

configuration/checkers.tcl

@@ -17,10 +17,7 @@ set ::env(QUIT_ON_ASSIGN_STATEMENTS) 0
 set ::env(QUIT_ON_UNMAPPED_CELLS) 1
 set ::env(QUIT_ON_SYNTH_CHECKS) 1
 set ::env(SYNTH_CHECKS_ALLOW_TRISTATE) 1
-set ::env(LINTER_RELATIVE_INCLUDES) 1
 set ::env(LINTER_INCLUDE_PDK_MODELS) 1
-set ::env(QUIT_ON_LINTER_WARNINGS) 0
-set ::env(QUIT_ON_LINTER_ERRORS) 1
 
 # STA
 set ::env(QUIT_ON_TIMING_VIOLATIONS) 1

configuration/floorplan.tcl

@@ -12,8 +12,6 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
-set ::env(DESIGN_IS_CORE) 1
-
 # Floorplan defaults
 set ::env(FP_SIZING) relative
 set ::env(FP_CORE_UTIL) 50
@@ -45,8 +43,6 @@ set ::env(TOP_MARGIN_MULT) 4
 set ::env(LEFT_MARGIN_MULT) 12
 set ::env(RIGHT_MARGIN_MULT) 12
 
-set ::env(FP_PDN_HORIZONTAL_HALO) 10
-set ::env(FP_PDN_VERTICAL_HALO) $::env(FP_PDN_HORIZONTAL_HALO)
 set ::env(FP_TAP_HORIZONTAL_HALO) 10
 set ::env(FP_TAP_VERTICAL_HALO) $::env(FP_TAP_HORIZONTAL_HALO)
 set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) 1

configuration/general.tcl

@@ -15,7 +15,6 @@
 # General Defaults
 set ::env(CLOCK_PERIOD) "10.0"
 set ::env(USE_GPIO_PADS) 0
-set ::env(RSZ_DONT_TOUCH_RX) "$^"
 set ::env(RSZ_MULTICORNER_LIB) 1
 set ::env(RSZ_DONT_TOUCH) ""
 
@@ -41,7 +40,6 @@ set ::env(RUN_IRDROP_REPORT) 1
 
 ## Signoff
 set ::env(RUN_CVC) 1
-set ::env(PRIMARY_GDSII_STREAMOUT_TOOL) magic
 
 ### Netgen
 set ::env(RUN_LVS) 1

configuration/synthesis.tcl

@@ -28,7 +28,6 @@ set ::env(SYNTH_STRATEGY) "AREA 0"
 set ::env(SYNTH_ADDER_TYPE) "YOSYS"
 set ::env(CLOCK_BUFFER_FANOUT) 16
 set ::env(SYNTH_READ_BLACKBOX_LIB) 0
-set ::env(SYNTH_ELABORATE_ONLY) 0
 set ::env(SYNTH_FLAT_TOP) 0
 set ::env(IO_PCT) 0.2
 set ::env(SYNTH_EXTRA_MAPPING_FILE) ""

designs/spm/config.json

@@ -1,30 +1,30 @@
 {
+    "//": "Basics",
     "DESIGN_NAME": "spm",
     "VERILOG_FILES": "dir::src/*.v",
     "CLOCK_PERIOD": 10,
     "CLOCK_PORT": "clk",
-    "CLOCK_NET": "ref::$CLOCK_PORT",
-    "FP_PDN_VOFFSET": 7,
-    "FP_PDN_HOFFSET": 7,
-    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+    "PNR_SDC_FILE": "dir::src/spm.sdc",
+    "SIGNOFF_SDC_FILE": "dir::src/spm.sdc",
+    "//": "PDN",
+    "FP_PDN_VOFFSET": 5,
+    "FP_PDN_HOFFSET": 5,
+    "FP_PDN_VWIDTH": 2,
+    "FP_PDN_HWIDTH": 2,
+    "FP_PDN_VPITCH": 30,
+    "FP_PDN_HPITCH": 30,
     "FP_PDN_SKIPTRIM": true,
+    "//": "Pin Order",
+    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+    "//": "Technology-Specific Configs",
     "pdk::sky130*": {
         "FP_CORE_UTIL": 45,
-        "scl::sky130_fd_sc_hd": {
-            "CLOCK_PERIOD": 10
-        },
-        "scl::sky130_fd_sc_hdll": {
-            "CLOCK_PERIOD": 10
-        },
+        "CLOCK_PERIOD": 10,
         "scl::sky130_fd_sc_hs": {
             "CLOCK_PERIOD": 8
         },
         "scl::sky130_fd_sc_ls": {
-            "CLOCK_PERIOD": 10,
             "MAX_FANOUT_CONSTRAINT": 5
-        },
-        "scl::sky130_fd_sc_ms": {
-            "CLOCK_PERIOD": 10
         }
     },
     "pdk::gf180mcu*": {

designs/spm/pin_order.cfg

@@ -1,6 +1,6 @@
 #N
 @min_distance=0.1
-x.*
+a.*
 
 #S
 $1
@@ -10,5 +10,5 @@ rst
 clk
 
 #W
-p
 y
+x

designs/spm/src/spm.sdc

@@ -1,2 +1,2 @@
 set_units -time ns
-create_clock [get_ports clk]  -name core_clock  -period 10
+create_clock [get_ports clk]  -name core_clock -period 10

designs/spm/src/spm.v

@@ -1,4 +1,4 @@
-// Copyright 2020 Efabless Corporation
+// Copyright 2023 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -12,130 +12,61 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-module spm(clk, rst, x, y, p);
-    parameter size = 32;
-    input clk, rst;
-    input y;
-    input[size-1:0] x;
-    output p;
+// (Parameterized) Unsigned Serial/Parallel Multiplier:
+// - Multiplicand x (Input bit-serially)
+// - Multiplier a (All bits at the same time/Parallel)
+// - Product y (Output bit-serial)
+module spm #(parameter bits=32) (
+    input clk,
+    input rst,
+    input x,
+    input[bits-1: 0] a,
+    output y
+);
+    wire[bits: 0] y_chain;
+    assign y_chain[0] = 0;
+    assign y = y_chain[bits];
+
+    wire[bits-1:0] a_flip;
+    generate 
+        for (genvar i = 0; i < bits; i = i + 1) begin : flip_block
+            assign a_flip[i] = a[bits - i - 1];
+        end 
+    endgenerate
+
+    delayed_serial_adder dsa[bits-1:0](
+        .clk(clk),
+        .rst(rst),
+        .x(x),
+        .a(a_flip),
+        .y_in(y_chain[bits-1:0]),
+        .y_out(y_chain[bits:1])
+    );
 
-    wire[size-1:1] pp;
-    wire[size-1:0] xy;
-
-    genvar i;
-
-    CSADD csa0 (.clk(clk), .rst(rst), .x(x[0]&y), .y(pp[1]), .sum(p));
-    generate for(i=1; i<size-1; i=i+1) begin
-        CSADD csa (.clk(clk), .rst(rst), .x(x[i]&y), .y(pp[i+1]), .sum(pp[i]));
-    end endgenerate
-    TCMP tcmp (.clk(clk), .rst(rst), .a(x[size-1]&y), .s(pp[size-1]));
-
-endmodule
-
-module TCMP(clk, rst, a, s);
-    input clk, rst;
-    input a;
-    output reg s;
-
-    reg z;
-
-    always @(posedge clk or posedge rst) begin
-        if (rst) begin
-            //Reset logic goes here.
-            s <= 1'b0;
-            z <= 1'b0;
-        end
-        else begin
-            //Sequential logic goes here.
-            z <= a | z;
-            s <= a ^ z;
-        end
-    end
 endmodule
 
-module CSADD(clk, rst, x, y, sum);
-    input clk, rst;
-    input x, y;
-    output reg sum;
-
-    reg sc;
-
-    // Half Adders logic
-    wire hsum1, hco1;
-    assign hsum1 = y ^ sc;
-    assign hco1 = y & sc;
-
-    wire hsum2, hco2;
-    assign hsum2 = x ^ hsum1;
-    assign hco2 = x & hsum1;
-
-    always @(posedge clk or posedge rst) begin
-        if (rst) begin
-            //Reset logic goes here.
-            sum <= 1'b0;
-            sc <= 1'b0;
-        end
-        else begin
-            //Sequential logic goes here.
-            sum <= hsum2;
-            sc <= hco1 ^ hco2;
+module delayed_serial_adder(
+    input clk,
+    input rst,
+    input x,
+    input a,
+    input y_in,
+    output reg y_out
+);
+    reg last_carry;
+    wire last_carry_next;
+    wire y_out_next;
+
+    wire g = x & a;
+    assign {last_carry_next, y_out_next} = g + y_in + last_carry;
+
+    always @ (posedge clk or negedge rst) begin
+        if (!rst) begin
+            last_carry <= 1'b0;
+            y_out <= 1'b0;
+        end else begin
+            last_carry <= last_carry_next;
+            y_out <= y_out_next;
         end
     end
 endmodule
-
-
-/*
-
-module spm_tb;
-
-	//Inputs
-	reg clk;
-	reg rst;
-	reg [7: 0] x;
-
-    reg[7:0] Y;
-    reg[15:0] P;
-
-	//Outputs
-	wire p;
-
-    reg[3:0] cnt;
-
-	//Instantiation of Unit Under Test
-	spm #(8) uut (
-		.clk(clk),
-		.rst(rst),
-		.y(Y[0]),
-		.x(x),
-		.p(p)
-	);
-
-    always #5 clk = ~clk;
-
-    always @ (posedge clk)
-        if(rst) Y = -50;
-        else Y <= {1'b0,Y[7:1]};
-
-    always @ (posedge clk)
-        if(rst) P = 0;
-        else P <= {p, P[15:1]};
-
-	always @ (posedge clk)
-        if(rst) cnt = 0;
-        else cnt <= cnt + 1;
-
-	initial begin
-	//Inputs initialization
-		clk = 0;
-		rst = 0;
-		x = 50;
-
-	//Reset
-		#20 rst = 1;
-		#20 rst = 0;
-        #1000;
-        $finish;
-	end
-
-endmodule
-*/