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synth: remove extract_fa #3087

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3f02e57
synth: remove extract_fa
widlarizer Apr 7, 2025
80f5e35
cells_adders: set techmap priority to 80
widlarizer Apr 7, 2025
eb1d9e9
synth: map adders with synth -extra-map
widlarizer Apr 7, 2025
119ff83
Bump yosys to PR #4997
widlarizer Apr 16, 2025
22090f9
fixup! Bump yosys to PR #4997
widlarizer Apr 16, 2025
8e72687
cells_adders: whitebox
widlarizer Apr 30, 2025
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2 changes: 1 addition & 1 deletion .gitmodules
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
[submodule "tools/yosys"]
path = tools/yosys
url = ../../The-OpenROAD-Project/yosys.git
url = https://github.com/YosysHQ/yosys.git
[submodule "tools/OpenROAD"]
path = tools/OpenROAD
url = ../OpenROAD.git
4 changes: 2 additions & 2 deletions flow/platforms/asap7/yoSys/cells_adders_L.v
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@@ -1,6 +1,6 @@

(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
module _80_tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
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4 changes: 2 additions & 2 deletions flow/platforms/asap7/yoSys/cells_adders_R.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@

(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
module _80_tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
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4 changes: 2 additions & 2 deletions flow/platforms/asap7/yoSys/cells_adders_SL.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@

(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
module _80_tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
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4 changes: 2 additions & 2 deletions flow/platforms/gf180/cells_adders.v
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@@ -1,6 +1,6 @@

(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
module _80_tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
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4 changes: 2 additions & 2 deletions flow/platforms/nangate45/cells_adders.v
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@@ -1,6 +1,6 @@

(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
module _80_tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
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4 changes: 2 additions & 2 deletions flow/platforms/sky130hd/cells_adders_hd.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@

(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
module _80_tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
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4 changes: 2 additions & 2 deletions flow/platforms/sky130hs/cells_adders_hs.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@

(* techmap_celltype = "$fa" *)
module _tech_fa (A, B, C, X, Y);
(* abc9_box, lib_whitebox, techmap_celltype = "$fa" *)
module _80_tech_fa (A, B, C, X, Y);
parameter WIDTH = 1;
(* force_downto *)
input [WIDTH-1 : 0] A, B, C;
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17 changes: 6 additions & 11 deletions flow/scripts/synth.tcl
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Expand Up @@ -22,7 +22,13 @@ set synth_full_args $::env(SYNTH_ARGS)
if {[env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS]} {
set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)]
} else {
# Coarse LCU -> Kogge-Stone
set synth_full_args [concat $synth_full_args "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"]

if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} {
# Coarse FA -> PDK FA
set synth_full_args [concat $synth_full_args "-extra-map $::env(ADDER_MAP_FILE)"]
}
}

if {![env_var_equals SYNTH_HIERARCHICAL 1]} {
Expand Down Expand Up @@ -70,17 +76,6 @@ renames -wire
# Optimize the design
opt -purge

# Technology mapping of adders
if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} {
# extract the full adders
extract_fa
# map full adders
techmap -map $::env(ADDER_MAP_FILE)
techmap
# Quick optimization
opt -fast -purge
}

# Technology mapping of latches
if {[env_var_exists_and_non_empty LATCH_MAP_FILE]} {
techmap -map $::env(LATCH_MAP_FILE)
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2 changes: 1 addition & 1 deletion tools/yosys
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Submodule yosys updated 31 files
+2 −0 .gitignore
+3 −0 CHANGELOG
+2 −2 Makefile
+22 −0 backends/aiger/xaiger.cc
+1 −1 backends/cxxrtl/cxxrtl_backend.cc
+1 −1 docs/source/cell/word_arith.rst
+1 −1 docs/source/code_examples/fifo/fifo.ys
+3 −0 docs/source/conf.py
+1 −1 docs/source/getting_started/example_synth.rst
+7 −3 frontends/verific/verific.cc
+87 −0 frontends/verilog/verilog_frontend.cc
+1 −1 kernel/celledges.cc
+1 −0 kernel/celltypes.h
+1 −1 kernel/consteval.h
+8 −0 kernel/constids.inc
+5 −4 kernel/fmt.cc
+112 −36 kernel/macc.h
+45 −0 kernel/rtlil.cc
+2 −0 kernel/rtlil.h
+1 −1 kernel/satgen.cc
+1 −2 passes/cmds/splitcells.cc
+41 −3 passes/opt/share.cc
+1 −1 passes/techmap/booth.cc
+1 −1 passes/techmap/maccmap.cc
+4 −4 passes/techmap/techmap.cc
+114 −0 techlibs/common/simlib.v
+10 −3 techlibs/common/techmap.v
+1 −1 techlibs/gowin/cells_sim.v
+61 −0 tests/alumacc/basic.ys
+19 −0 tests/alumacc/macc_infer_n_unmap.ys
+44 −0 tests/various/bug4909.ys