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Merged
merged 19 commits into from
Oct 2, 2025
Merged

New VT swap for critical cells near end of setup fixing #8378

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5732a8b
added VT swap for critical cells near end of setup fixing
precisionmoon Sep 9, 2025
b9c8cc1
fixed clang-tidy and clang-format + bazel build issue
precisionmoon Sep 9, 2025
1426a0c
clang-format fix
precisionmoon Sep 9, 2025
678dd7e
added -skip_crit_vt_swap option
precisionmoon Sep 17, 2025
b12a532
Merge remote-tracking branch 'origin/master' into secure-setup-qor
precisionmoon Sep 17, 2025
85ab85b
replaced findPathEnds for critical VT swap with topological search
precisionmoon Sep 19, 2025
af7006d
Merge remote-tracking branch 'origin/master' into secure-setup-qor
precisionmoon Sep 19, 2025
773ce33
clang-tidy fix
precisionmoon Sep 19, 2025
a1a6d3e
added doc for -skip_crit_vt_swap
precisionmoon Sep 20, 2025
a5073ec
added missing SDC flie for one test
precisionmoon Sep 20, 2025
687e2d5
Merge remote-tracking branch 'origin/master' into secure-setup-qor
precisionmoon Sep 23, 2025
7dcbad4
Merge remote-tracking branch 'origin/master' into secure-setup-qor
precisionmoon Sep 29, 2025
29a2561
Merge branch 'secure-setup-qor' of github.com:The-OpenROAD-Project-pr…
precisionmoon Sep 29, 2025
5535f3a
added additional slack check for bidi split pins
precisionmoon Sep 29, 2025
9c9c6f4
updated instance slack query
precisionmoon Sep 30, 2025
ef188a0
Merge remote-tracking branch 'origin/master' into secure-setup-qor
precisionmoon Sep 30, 2025
3ea8c50
resolved merge conflict
precisionmoon Sep 30, 2025
5f14e15
incorporated code review feedback from Martin
precisionmoon Sep 30, 2025
a79bac9
rsz: buildifier rsz/test/BUILD
maliberty Oct 1, 2025
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116 changes: 58 additions & 58 deletions src/gpl/test/convergence01.defok
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Original file line number Diff line number Diff line change
Expand Up @@ -161,70 +161,70 @@ COMPONENTS 145 ;
- PHY_8 TAPCELL_ASAP7_75t_R + SOURCE DIST + FIXED ( 486 1620 ) N ;
- PHY_9 TAPCELL_ASAP7_75t_R + SOURCE DIST + FIXED ( 11394 1620 ) FN ;
- _33_ INVx3_ASAP7_75t_R + PLACED ( 4853 10251 ) N ;
- _34_ INVx3_ASAP7_75t_R + PLACED ( 5471 6131 ) N ;
- _35_ INVx3_ASAP7_75t_R + PLACED ( 5187 5909 ) N ;
- _36_ INVx3_ASAP7_75t_R + PLACED ( 4338 10251 ) N ;
- _37_ INVx3_ASAP7_75t_R + PLACED ( 4723 5498 ) N ;
- _38_ INVx3_ASAP7_75t_R + PLACED ( 4573 5470 ) N ;
- _39_ INVx3_ASAP7_75t_R + PLACED ( 10394 4180 ) N ;
- _40_ INVx3_ASAP7_75t_R + PLACED ( 6094 4723 ) N ;
- _41_ INVx3_ASAP7_75t_R + PLACED ( 10394 4326 ) N ;
- _42_ INVx3_ASAP7_75t_R + PLACED ( 5878 4326 ) N ;
- _43_ INVx3_ASAP7_75t_R + PLACED ( 5826 4162 ) N ;
- _34_ INVx3_ASAP7_75t_R + PLACED ( 5471 6127 ) N ;
- _35_ INVx3_ASAP7_75t_R + PLACED ( 5187 5904 ) N ;
- _36_ INVx3_ASAP7_75t_R + PLACED ( 4333 10251 ) N ;
- _37_ INVx3_ASAP7_75t_R + PLACED ( 4722 5500 ) N ;
- _38_ INVx3_ASAP7_75t_R + PLACED ( 4571 5476 ) N ;
- _39_ INVx3_ASAP7_75t_R + PLACED ( 10394 4195 ) N ;
- _40_ INVx3_ASAP7_75t_R + PLACED ( 6094 4724 ) N ;
- _41_ INVx3_ASAP7_75t_R + PLACED ( 10394 4338 ) N ;
- _42_ INVx3_ASAP7_75t_R + PLACED ( 5878 4328 ) N ;
- _43_ INVx3_ASAP7_75t_R + PLACED ( 5825 4163 ) N ;
- _44_ INVx3_ASAP7_75t_R + PLACED ( 10394 3755 ) N ;
- _45_ INVx3_ASAP7_75t_R + PLACED ( 5701 3926 ) N ;
- _46_ INVx3_ASAP7_75t_R + PLACED ( 5635 3850 ) N ;
- _47_ INVx3_ASAP7_75t_R + PLACED ( 3023 1359 ) N ;
- _48_ INVx3_ASAP7_75t_R + PLACED ( 2936 1359 ) N ;
- _45_ INVx3_ASAP7_75t_R + PLACED ( 5702 3927 ) N ;
- _46_ INVx3_ASAP7_75t_R + PLACED ( 5637 3851 ) N ;
- _47_ INVx3_ASAP7_75t_R + PLACED ( 3021 1359 ) N ;
- _48_ INVx3_ASAP7_75t_R + PLACED ( 2934 1359 ) N ;
- _49_ INVx3_ASAP7_75t_R + PLACED ( 2845 1359 ) N ;
- _50_ INVx3_ASAP7_75t_R + PLACED ( 2753 1359 ) N ;
- _51_ INVx3_ASAP7_75t_R + PLACED ( 2687 1359 ) N ;
- _52_ INVx3_ASAP7_75t_R + PLACED ( 2637 1359 ) N ;
- _52_ INVx3_ASAP7_75t_R + PLACED ( 2638 1359 ) N ;
- _53_ INVx3_ASAP7_75t_R + PLACED ( 2590 1359 ) N ;
- _54_ INVx3_ASAP7_75t_R + PLACED ( 2542 1359 ) N ;
- _55_ INVx3_ASAP7_75t_R + PLACED ( 4012 3943 ) N ;
- _56_ INVx3_ASAP7_75t_R + PLACED ( 3893 3809 ) N ;
- _57_ INVx3_ASAP7_75t_R + PLACED ( 3853 3613 ) N ;
- _58_ INVx3_ASAP7_75t_R + PLACED ( 3865 3349 ) N ;
- _59_ INVx3_ASAP7_75t_R + PLACED ( 3974 3057 ) N ;
- _60_ INVx3_ASAP7_75t_R + PLACED ( 3979 2937 ) N ;
- _61_ INVx3_ASAP7_75t_R + PLACED ( 3378 2964 ) N ;
- _62_ INVx3_ASAP7_75t_R + PLACED ( 2081 2989 ) N ;
- _63_ INVx3_ASAP7_75t_R + PLACED ( 5936 6433 ) N ;
- _64_ INVx3_ASAP7_75t_R + PLACED ( 5906 6298 ) N ;
- _65_ INVx3_ASAP7_75t_R + PLACED ( 5760 6213 ) N ;
- _66_ DFFLQNx1_ASAP7_75t_R + PLACED ( 6017 5377 ) N ;
- _67_ DFFLQNx1_ASAP7_75t_R + PLACED ( 6143 5475 ) N ;
- _68_ DFFLQNx1_ASAP7_75t_R + PLACED ( 6135 5621 ) N ;
- _69_ DFFLQNx1_ASAP7_75t_R + PLACED ( 1890 1451 ) N ;
- _70_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3197 1472 ) N ;
- _71_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3563 1585 ) N ;
- _72_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3635 1905 ) N ;
- _73_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3627 2322 ) N ;
- _74_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3668 2724 ) N ;
- _75_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3715 2997 ) N ;
- _76_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3827 3170 ) N ;
- _77_ DFFLQNx1_ASAP7_75t_R + PLACED ( 919 2064 ) N ;
- _78_ DFFLQNx1_ASAP7_75t_R + PLACED ( 919 2084 ) N ;
- _79_ DFFLQNx1_ASAP7_75t_R + PLACED ( 919 2098 ) N ;
- _80_ DFFLQNx1_ASAP7_75t_R + PLACED ( 935 2099 ) N ;
- _81_ DFFLQNx1_ASAP7_75t_R + PLACED ( 976 2101 ) N ;
- _82_ DFFLQNx1_ASAP7_75t_R + PLACED ( 1045 2163 ) N ;
- _83_ DFFLQNx1_ASAP7_75t_R + PLACED ( 1134 2552 ) N ;
- _84_ DFFLQNx1_ASAP7_75t_R + PLACED ( 1202 3049 ) N ;
- _85_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3710 4615 ) N ;
- _86_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3803 4668 ) N ;
- _87_ DFFLQNx1_ASAP7_75t_R + PLACED ( 9224 3636 ) N ;
- _88_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3967 4956 ) N ;
- _89_ DFFLQNx1_ASAP7_75t_R + PLACED ( 4041 5205 ) N ;
- _90_ DFFLQNx1_ASAP7_75t_R + PLACED ( 8803 4914 ) N ;
- _54_ INVx3_ASAP7_75t_R + PLACED ( 2543 1359 ) N ;
- _55_ INVx3_ASAP7_75t_R + PLACED ( 4001 3943 ) N ;
- _56_ INVx3_ASAP7_75t_R + PLACED ( 3884 3810 ) N ;
- _57_ INVx3_ASAP7_75t_R + PLACED ( 3846 3617 ) N ;
- _58_ INVx3_ASAP7_75t_R + PLACED ( 3860 3351 ) N ;
- _59_ INVx3_ASAP7_75t_R + PLACED ( 3971 3055 ) N ;
- _60_ INVx3_ASAP7_75t_R + PLACED ( 3971 2934 ) N ;
- _61_ INVx3_ASAP7_75t_R + PLACED ( 3379 2962 ) N ;
- _62_ INVx3_ASAP7_75t_R + PLACED ( 2091 2990 ) N ;
- _63_ INVx3_ASAP7_75t_R + PLACED ( 5935 6431 ) N ;
- _64_ INVx3_ASAP7_75t_R + PLACED ( 5905 6296 ) N ;
- _65_ INVx3_ASAP7_75t_R + PLACED ( 5762 6209 ) N ;
- _66_ DFFLQNx1_ASAP7_75t_R + PLACED ( 6021 5372 ) N ;
- _67_ DFFLQNx1_ASAP7_75t_R + PLACED ( 6140 5473 ) N ;
- _68_ DFFLQNx1_ASAP7_75t_R + PLACED ( 6135 5617 ) N ;
- _69_ DFFLQNx1_ASAP7_75t_R + PLACED ( 1903 1453 ) N ;
- _70_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3200 1468 ) N ;
- _71_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3559 1580 ) N ;
- _72_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3634 1899 ) N ;
- _73_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3625 2324 ) N ;
- _74_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3665 2729 ) N ;
- _75_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3710 2997 ) N ;
- _76_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3821 3170 ) N ;
- _77_ DFFLQNx1_ASAP7_75t_R + PLACED ( 919 2062 ) N ;
- _78_ DFFLQNx1_ASAP7_75t_R + PLACED ( 919 2083 ) N ;
- _79_ DFFLQNx1_ASAP7_75t_R + PLACED ( 919 2096 ) N ;
- _80_ DFFLQNx1_ASAP7_75t_R + PLACED ( 935 2098 ) N ;
- _81_ DFFLQNx1_ASAP7_75t_R + PLACED ( 975 2099 ) N ;
- _82_ DFFLQNx1_ASAP7_75t_R + PLACED ( 1043 2161 ) N ;
- _83_ DFFLQNx1_ASAP7_75t_R + PLACED ( 1131 2547 ) N ;
- _84_ DFFLQNx1_ASAP7_75t_R + PLACED ( 1200 3048 ) N ;
- _85_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3711 4617 ) N ;
- _86_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3804 4669 ) N ;
- _87_ DFFLQNx1_ASAP7_75t_R + PLACED ( 9222 3637 ) N ;
- _88_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3966 4958 ) N ;
- _89_ DFFLQNx1_ASAP7_75t_R + PLACED ( 4040 5208 ) N ;
- _90_ DFFLQNx1_ASAP7_75t_R + PLACED ( 8792 4940 ) N ;
- _91_ DFFLQNx1_ASAP7_75t_R + PLACED ( 4277 5992 ) N ;
- _92_ DFFLQNx1_ASAP7_75t_R + PLACED ( 9047 4443 ) N ;
- _93_ DFFLQNx1_ASAP7_75t_R + PLACED ( 4255 4689 ) N ;
- _94_ DFFLQNx1_ASAP7_75t_R + PLACED ( 4453 4741 ) N ;
- _95_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3529 10003 ) N ;
- _96_ DFFLQNx1_ASAP7_75t_R + PLACED ( 5154 5069 ) N ;
- _97_ DFFLQNx1_ASAP7_75t_R + PLACED ( 5559 5278 ) N ;
- _92_ DFFLQNx1_ASAP7_75t_R + PLACED ( 9028 4475 ) N ;
- _93_ DFFLQNx1_ASAP7_75t_R + PLACED ( 4250 4693 ) N ;
- _94_ DFFLQNx1_ASAP7_75t_R + PLACED ( 4451 4742 ) N ;
- _95_ DFFLQNx1_ASAP7_75t_R + PLACED ( 3520 10008 ) N ;
- _96_ DFFLQNx1_ASAP7_75t_R + PLACED ( 5154 5064 ) N ;
- _97_ DFFLQNx1_ASAP7_75t_R + PLACED ( 5560 5272 ) N ;
END COMPONENTS
PINS 65 ;
- clock + NET clock + DIRECTION INPUT + USE SIGNAL
Expand Down
60 changes: 30 additions & 30 deletions src/gpl/test/convergence01.ok
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Expand Up @@ -80,37 +80,37 @@ Iteration | Area | Resized | Buffers | Nets repaired | Remaining
[INFO GPL-0110] Timing-driven: new target density: 0.5
Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group
---------------------------------------------------------------
10 | 0.1852 | 4.010190e+02 | +0.78% | 1.22e-10 |
20 | 0.1983 | 3.996960e+02 | -0.33% | 1.80e-10 |
30 | 0.2139 | 3.996910e+02 | -0.00% | 2.66e-10 |
40 | 0.2224 | 3.997260e+02 | +0.01% | 3.91e-10 |
50 | 0.2072 | 3.997480e+02 | +0.01% | 5.76e-10 |
60 | 0.2037 | 3.997340e+02 | -0.00% | 8.49e-10 |
70 | 0.1996 | 3.996970e+02 | -0.01% | 1.25e-09 |
80 | 0.2094 | 3.997010e+02 | +0.00% | 1.84e-09 |
90 | 0.2069 | 3.997450e+02 | +0.01% | 2.71e-09 |
100 | 0.2129 | 3.997350e+02 | -0.00% | 4.00e-09 |
110 | 0.2057 | 3.997330e+02 | -0.00% | 5.89e-09 |
120 | 0.2047 | 3.997140e+02 | -0.00% | 8.68e-09 |
130 | 0.2001 | 3.997150e+02 | +0.00% | 1.28e-08 |
140 | 0.2082 | 3.997060e+02 | -0.00% | 1.88e-08 |
150 | 0.2041 | 3.997320e+02 | +0.01% | 2.77e-08 |
160 | 0.2099 | 3.997370e+02 | +0.00% | 4.09e-08 |
170 | 0.2035 | 3.998120e+02 | +0.02% | 6.02e-08 |
180 | 0.1994 | 3.998580e+02 | +0.01% | 8.87e-08 |
190 | 0.1909 | 3.999030e+02 | +0.01% | 1.31e-07 |
200 | 0.2047 | 3.997060e+02 | -0.05% | 1.92e-07 |
210 | 0.1996 | 3.998090e+02 | +0.03% | 2.83e-07 |
220 | 0.1939 | 3.999210e+02 | +0.03% | 4.18e-07 |
230 | 0.1812 | 3.998690e+02 | -0.01% | 6.15e-07 |
240 | 0.1842 | 3.997750e+02 | -0.02% | 9.06e-07 |
250 | 0.1788 | 3.998360e+02 | +0.02% | 1.33e-06 |
260 | 0.1719 | 3.998900e+02 | +0.01% | 1.97e-06 |
270 | 0.1622 | 3.998190e+02 | -0.02% | 2.90e-06 |
10 | 0.1870 | 4.009940e+02 | +0.78% | 1.22e-10 |
20 | 0.1988 | 3.997030e+02 | -0.32% | 1.80e-10 |
30 | 0.2140 | 3.996830e+02 | -0.01% | 2.66e-10 |
40 | 0.2231 | 3.997220e+02 | +0.01% | 3.91e-10 |
50 | 0.2084 | 3.997420e+02 | +0.01% | 5.76e-10 |
60 | 0.2024 | 3.997290e+02 | -0.00% | 8.49e-10 |
70 | 0.1990 | 3.996960e+02 | -0.01% | 1.25e-09 |
80 | 0.2103 | 3.996920e+02 | -0.00% | 1.84e-09 |
90 | 0.2071 | 3.997460e+02 | +0.01% | 2.71e-09 |
100 | 0.2133 | 3.997360e+02 | -0.00% | 4.00e-09 |
110 | 0.2051 | 3.997290e+02 | -0.00% | 5.89e-09 |
120 | 0.2047 | 3.997080e+02 | -0.01% | 8.68e-09 |
130 | 0.1994 | 3.997140e+02 | +0.00% | 1.28e-08 |
140 | 0.2093 | 3.997020e+02 | -0.00% | 1.88e-08 |
150 | 0.2039 | 3.997340e+02 | +0.01% | 2.77e-08 |
160 | 0.2097 | 3.997340e+02 | +0.00% | 4.09e-08 |
170 | 0.2033 | 3.998010e+02 | +0.02% | 6.02e-08 |
180 | 0.1991 | 3.998550e+02 | +0.01% | 8.87e-08 |
190 | 0.1917 | 3.999040e+02 | +0.01% | 1.31e-07 |
200 | 0.2051 | 3.997040e+02 | -0.05% | 1.92e-07 |
210 | 0.1982 | 3.998130e+02 | +0.03% | 2.83e-07 |
220 | 0.1939 | 3.999100e+02 | +0.02% | 4.18e-07 |
230 | 0.1813 | 3.998720e+02 | -0.01% | 6.15e-07 |
240 | 0.1841 | 3.997760e+02 | -0.02% | 9.06e-07 |
250 | 0.1791 | 3.998330e+02 | +0.01% | 1.33e-06 |
260 | 0.1719 | 3.998860e+02 | +0.01% | 1.97e-06 |
270 | 0.1622 | 3.998120e+02 | -0.02% | 2.90e-06 |
280 | 0.1421 | 3.998290e+02 | +0.00% | 4.27e-06 |
290 | 0.1288 | 3.999540e+02 | +0.03% | 6.29e-06 |
300 | 0.1138 | 4.000310e+02 | +0.02% | 9.26e-06 |
308 | 0.0995 | 4.002340e+02 | | 1.31e-05 |
290 | 0.1288 | 3.999560e+02 | +0.03% | 6.29e-06 |
300 | 0.1141 | 4.000290e+02 | +0.02% | 9.26e-06 |
308 | 0.0995 | 4.002280e+02 | | 1.31e-05 |
---------------------------------------------------------------
[INFO GPL-1001] Global placement finished at iteration 308
[INFO GPL-1002] Placed Cell Area 15.5277
Expand Down
8 changes: 4 additions & 4 deletions src/psm/test/aes_asap7_vdd.ok
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Original file line number Diff line number Diff line change
Expand Up @@ -21,9 +21,9 @@
Net : VDD
Corner : default
Supply voltage : 7.00e-01 V
Worstcase voltage: 6.93e-01 V
Worstcase voltage: 6.91e-01 V
Average voltage : 6.97e-01 V
Average IR drop : 2.65e-03 V
Worstcase IR drop: 6.60e-03 V
Percentage drop : 0.94 %
Average IR drop : 3.37e-03 V
Worstcase IR drop: 8.55e-03 V
Percentage drop : 1.22 %
######################################
2 changes: 2 additions & 0 deletions src/rsz/README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -231,6 +231,7 @@ repair_timing
[-skip_buffer_removal]
[-skip_last_gasp]
[-skip_vt_swap]
[-skip_crit_vt_swap]
[-repair_tns tns_end_percent]
[-max_passes passes]
[-max_repairs_per_pass max_repairs_per_pass]
Expand Down Expand Up @@ -258,6 +259,7 @@ repair_timing
| `-skip_buffer_removal` | Flag to skip buffer removal. The default is to perform buffer removal transform during setup fixing. |
| `-skip_last_gasp` | Flag to skip final ("last gasp") optimizations. The default is to perform greedy sizing at the end of optimization. |
| `-skip_vt_swap` | Flag to skip threshold voltage (VT) swap optimizations. The default is to perform VT swap optimization to improve timing QoR. |
| `-skip_crit_vt_swap` | Flag to skip critical threshold voltage (VT) swap optimizations at the end of optimization. The default is to perform critical VT swap optimization to improve timing QoR beyond repairing just the worst path per each violating endpoint. |
| `-repair_tns` | Percentage of violating endpoints to repair (0-100). When `tns_end_percent` is zero, only the worst endpoint is repaired. When `tns_end_percent` is 100 (default), all violating endpoints are repaired. |
| `-max_repairs_per_pass` | Maximum repairs per pass, default is 1. On the worst paths, the maximum number of repairs is attempted. It gradually decreases until the final violations which only get 1 repair per pass. |
| `-max_utilization` | Defines the percentage of core area used. |
Expand Down
6 changes: 5 additions & 1 deletion src/rsz/include/rsz/Resizer.hh
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Original file line number Diff line number Diff line change
Expand Up @@ -286,7 +286,8 @@ class Resizer : public dbStaState, public dbNetworkObserver
bool skip_buffering,
bool skip_buffer_removal,
bool skip_last_gasp,
bool skip_vt_swap);
bool skip_vt_swap,
bool skip_crit_vt_swap);
// For testing.
void repairSetup(const Pin* end_pin);
// For testing.
Expand Down Expand Up @@ -684,6 +685,9 @@ class Resizer : public dbStaState, public dbNetworkObserver
bool isLogicStdCell(const Instance* inst);

bool okToBufferNet(const Pin* driver_pin) const;
bool checkAndMarkVTSwappable(Instance* inst,
std::unordered_set<Instance*>& notSwappable,
LibertyCell*& best_lib_cell);

////////////////////////////////////////////////////////////////
// Jounalling support for checkpointing and backing out changes
Expand Down
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