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megaboom: branch predictors as macros #210

Merged
merged 2 commits into from
Nov 21, 2024
Merged

megaboom: branch predictors as macros #210

merged 2 commits into from
Nov 21, 2024

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oharboe
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@oharboe oharboe commented Nov 19, 2024

Branch predictor macros visible:

image

WNS from gui_floorplan:

image

Stage: cts

Variant base 1
Description Flattend, timing driven placement Hierarchical, branch predictors as macros
Buffer 118586 246303
Clock buffer 12894 20569
Clock inverter 3737 5945
Inverter 70385 130946
Macro 72 42
Multi-Input combinational cell 740179 1263033
Sequential cell 118443 214014
Tie cell 60 1520
Timing Repair Buffer 48326 72251
Total 1112682 1954623
slack -2872.979248 -4737.364746
tns -95525616.0 -359412736.0
GPL_TIMING_DRIVEN 1
HOLD_SLACK_MARGIN -900
MACRO_PLACEMENT_TCL $(location write_macro_placement)
MAX_ROUTING_LAYER M9
PDN_TCL $(location :pdn.tcl)
SKIP_CTS_REPAIR_TIMING 0
SKIP_LAST_GASP 0
SYNTH_HIERARCHICAL 0
dissolve
previous_stage
2_1_floorplan.log 148 534
2_2_floorplan_io.log 21 35
2_3_floorplan_macro.log 25 918
2_4_floorplan_tapcell.log 21 32
2_5_floorplan_pdn.log 721 203
3_1_place_gp_skip_io.log 2224 1800
3_2_place_iop.log 28 42
3_3_place_gp.log 13303 3411
3_4_place_resized.log 310 544
3_5_place_dp.log 840 1368
4_1_cts.log 1801 495

Base configuration variables

Variable Value
CORE_AREA 2 2 1998 1998
DIE_AREA 0 0 2000 2000
FILL_CELLS
GPL_ROUTABILITY_DRIVEN 1
GPL_TIMING_DRIVEN 0
HOLD_SLACK_MARGIN -200
IO_CONSTRAINTS $(location :io-boomtile)
MACRO_PLACE_HALO 19 19
MAX_ROUTING_LAYER M7
MIN_ROUTING_LAYER M2
PDN_TCL $(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl
PLACE_DENSITY 0.24
PLACE_PINS_ARGS -annealing
ROUTING_LAYER_ADJUSTMENT 0.45
SDC_FILE $(location :constraints-boomtile)
SETUP_SLACK_MARGIN -1300
SKIP_CTS_REPAIR_TIMING 1
SKIP_INCREMENTAL_REPAIR 1
SKIP_LAST_GASP 1
SKIP_REPORT_METRICS 1
SYNTH_HIERARCHICAL 1
TAPCELL_TCL
TNS_END_PERCENT 0

@oharboe oharboe force-pushed the branch-predictor-macro branch 2 times, most recently from 1d6cd0b to d314013 Compare November 19, 2024 20:22
Signed-off-by: Øyvind Harboe <[email protected]>
@oharboe oharboe force-pushed the branch-predictor-macro branch 3 times, most recently from 77e30b8 to a316de8 Compare November 20, 2024 09:28
@oharboe
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oharboe commented Nov 20, 2024

@maliberty @jeffng-or When I create macros for the branch predictors, the floorplan looks much better:

Macros are now in four groups:

  • data cache
  • instruction cache
  • branch predictors
  • register files

I'm using mock-area for branch predictors on one hand, but I have not put any effort to figuring out what size they need to be. I'm thinking the area should now be possible to bring down to something near 1000x1000um.

@oharboe oharboe force-pushed the branch-predictor-macro branch from a316de8 to ea54066 Compare November 20, 2024 14:53
@oharboe oharboe force-pushed the branch-predictor-macro branch from ea54066 to f97700f Compare November 20, 2024 18:47
@oharboe
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oharboe commented Nov 21, 2024

@jeffng-or @maliberty While interesting that branch predictors as macros clean up the top level floorplan as much as it does, WNS goes from -2872.979248 to -4737.364746. I'm going to keep the additional code I wrote, but I'm not switching to branch predictors as macros.

There's a chance that the WNS stems from the suboptimal Branch Predictor macro and that the branch predictor macro can be significantly improved, but I plan to let that lie.

@oharboe oharboe merged commit 3a3b396 into main Nov 21, 2024
2 of 3 checks passed
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oharboe commented Nov 21, 2024

@maliberty @jeffng-or 1500x1500 layout, looks neat and clean now that branch predictors are off to the side as macros.

Upon closer inspection: I'm not sure that it is such a bad idea to have the branch predictors as macros. It would need some further exploration. Hard to tell without better synthesis(levels of logic should probably be closer to 20 to compete with commerical tools ref. 28nm 1000ps tapeout of BOOM).

image

image

image

image

@oharboe
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oharboe commented Nov 21, 2024

@maliberty @jeffng-or WNS coming or going from branch predictors is -2200, which isn't horrible. Perhaps put both branch predictors into a single macro? There's paths from branch 0 going into branch predictor 1, so they are intertwined in some way.

>>> report_checks -from frontend/bpd/banked_predictors_0
Startpoint: frontend/bpd/banked_predictors_0
            (rising edge-triggered flip-flop clocked by clock)
Endpoint: frontend/icache/dataArrayB0Way_3_ext
          (rising edge-triggered flip-flop clocked by clock)
Path Group: reg2reg
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
1347.52 1347.52   clock network delay (propagated)
   0.00 1347.52 ^ frontend/bpd/banked_predictors_0/clock (ComposedBranchPredictorBank)
1047.38 2394.90 v frontend/bpd/banked_predictors_0/io_resp_f3_2_taken (ComposedBranchPredictorBank)
  61.56 2456.47 v wire72139/Y (BUFx16f_ASAP7_75t_R)
  47.53 2503.99 v frontend/bpd/_5978_/Y (AND2x2_ASAP7_75t_R)
  22.19 2526.19 v frontend/bpd/_5979_/Y (AO21x2_ASAP7_75t_R)
  19.33 2545.52 v frontend/f3_bpd_resp/_6400_/Y (AND2x2_ASAP7_75t_R)
  28.19 2573.71 v frontend/f3_bpd_resp/_6401_/Y (AO21x2_ASAP7_75t_R)
  32.49 2606.20 v frontend/_16497_/Y (OA21x2_ASAP7_75t_R)
  23.29 2629.49 v frontend/_16498_/Y (AO31x2_ASAP7_75t_R)
  28.48 2657.98 ^ frontend/_16691_/Y (NAND3x2_ASAP7_75t_R)
  48.96 2706.93 ^ frontend/_16692_/Y (AND4x2_ASAP7_75t_R)
  28.79 2735.72 v frontend/_16693_/Y (NAND2x2_ASAP7_75t_R)
  54.22 2789.94 v frontend/_17876_/Y (OR3x1_ASAP7_75t_R)
  20.24 2810.18 v frontend/_17877_/Y (BUFx6f_ASAP7_75t_R)
  51.93 2862.11 v frontend/_17894_/Y (OR4x2_ASAP7_75t_R)
  40.36 2902.48 v frontend/_18202_/Y (AND2x4_ASAP7_75t_R)
  19.82 2922.30 v frontend/_18242_/Y (AO21x1_ASAP7_75t_R)
  22.22 2944.52 v frontend/_18243_/Y (BUFx12_ASAP7_75t_R)
  15.84 2960.36 ^ frontend/_18244_/Y (CKINVDCx9p33_ASAP7_75t_R)
  25.29 2985.65 ^ frontend/_21982_/Y (BUFx10_ASAP7_75t_R)
  42.82 3028.47 v frontend/_23341_/Y (AOI211x1_ASAP7_75t_R)
  52.09 3080.56 ^ frontend/_23342_/Y (AOI22x1_ASAP7_75t_R)
  52.94 3133.50 v frontend/_23882_/Y (XNOR2x2_ASAP7_75t_R)
  43.89 3177.39 v frontend/_23885_/Y (OR4x2_ASAP7_75t_R)
  20.06 3197.45 v frontend/_23891_/Y (AO211x2_ASAP7_75t_R)
  32.32 3229.77 v frontend/_23915_/Y (OR4x1_ASAP7_75t_R)
  62.99 3292.76 v frontend/_23954_/Y (OR5x2_ASAP7_75t_R)
  43.03 3335.80 v frontend/_25630_/Y (AND2x6_ASAP7_75t_R)
  26.33 3362.13 v frontend/_28622_/Y (AND3x1_ASAP7_75t_R)
  46.38 3408.51 v frontend/_28624_/Y (OR3x4_ASAP7_75t_R)
  23.38 3431.89 v wire9941/Y (BUFx16f_ASAP7_75t_R)
  64.24 3496.13 v wire9940/Y (BUFx16f_ASAP7_75t_R)
  72.19 3568.32 v wire9939/Y (BUFx16f_ASAP7_75t_R)
  63.28 3631.61 v wire9938/Y (BUFx16f_ASAP7_75t_R)
  69.86 3701.47 v wire9937/Y (BUFx16f_ASAP7_75t_R)
  69.55 3771.01 v wire9936/Y (BUFx16f_ASAP7_75t_R)
  75.81 3846.83 v wire9935/Y (BUFx24_ASAP7_75t_R)
  74.67 3921.50 v wire9934/Y (BUFx24_ASAP7_75t_R)
  74.75 3996.25 v wire9933/Y (BUFx24_ASAP7_75t_R)
  76.84 4073.08 v frontend/icache/_6696_/Y (AND2x6_ASAP7_75t_R)
  18.43 4091.51 v max_length9604/Y (BUFx12f_ASAP7_75t_R)
  65.15 4156.67 v wire9603/Y (BUFx16f_ASAP7_75t_R)
  88.53 4245.19 v frontend/icache/_6715_/Y (AO21x2_ASAP7_75t_R)
  24.16 4269.35 v max_length9511/Y (BUFx12f_ASAP7_75t_R)
  62.37 4331.73 v wire9510/Y (BUFx10_ASAP7_75t_R)
  21.43 4353.15 v frontend/icache/dataArrayB0Way_3_ext/RW0_en (dataArrayB_256x64)
        4353.15   data arrival time

1200.00 1200.00   clock clock (rise edge)
1122.16 2322.16   clock network delay (propagated)
  13.66 2335.83   clock reconvergence pessimism
        2335.83 ^ frontend/icache/dataArrayB0Way_3_ext/RW0_clk (dataArrayB_256x64)
 -71.15 2264.68   library setup time
        2264.68   data required time
---------------------------------------------------------
        2264.68   data required time
        -4353.15   data arrival time
---------------------------------------------------------
        -2088.47   slack (VIOLATED)


>>> report_checks -to frontend/bpd/banked_predictors_0
Startpoint: frontend/bpd/banked_predictors_1
            (rising edge-triggered flip-flop clocked by clock)
Endpoint: frontend/bpd/banked_predictors_0
          (rising edge-triggered flip-flop clocked by clock)
Path Group: reg2reg
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
1592.70 1592.70   clock network delay (propagated)
   0.00 1592.70 ^ frontend/bpd/banked_predictors_1/clock (ComposedBranchPredictorBank)
1040.30 2633.00 v frontend/bpd/banked_predictors_1/io_resp_f3_2_taken (ComposedBranchPredictorBank)
  30.23 2663.23 v frontend/bpd/_5979_/Y (AO21x2_ASAP7_75t_R)
  19.33 2682.56 v frontend/f3_bpd_resp/_6400_/Y (AND2x2_ASAP7_75t_R)
  28.19 2710.76 v frontend/f3_bpd_resp/_6401_/Y (AO21x2_ASAP7_75t_R)
  32.49 2743.25 v frontend/_16497_/Y (OA21x2_ASAP7_75t_R)
  23.29 2766.54 v frontend/_16498_/Y (AO31x2_ASAP7_75t_R)
  28.48 2795.02 ^ frontend/_16691_/Y (NAND3x2_ASAP7_75t_R)
  48.96 2843.98 ^ frontend/_16692_/Y (AND4x2_ASAP7_75t_R)
  28.79 2872.77 v frontend/_16693_/Y (NAND2x2_ASAP7_75t_R)
  54.22 2926.99 v frontend/_17876_/Y (OR3x1_ASAP7_75t_R)
  20.24 2947.23 v frontend/_17877_/Y (BUFx6f_ASAP7_75t_R)
  51.93 2999.16 v frontend/_17894_/Y (OR4x2_ASAP7_75t_R)
  40.36 3039.52 v frontend/_18202_/Y (AND2x4_ASAP7_75t_R)
  19.82 3059.34 v frontend/_18242_/Y (AO21x1_ASAP7_75t_R)
  22.22 3081.57 v frontend/_18243_/Y (BUFx12_ASAP7_75t_R)
  15.84 3097.41 ^ frontend/_18244_/Y (CKINVDCx9p33_ASAP7_75t_R)
  25.29 3122.70 ^ frontend/_21982_/Y (BUFx10_ASAP7_75t_R)
  42.82 3165.52 v frontend/_23341_/Y (AOI211x1_ASAP7_75t_R)
  52.09 3217.61 ^ frontend/_23342_/Y (AOI22x1_ASAP7_75t_R)
  52.94 3270.55 v frontend/_23882_/Y (XNOR2x2_ASAP7_75t_R)
  43.89 3314.44 v frontend/_23885_/Y (OR4x2_ASAP7_75t_R)
  20.06 3334.50 v frontend/_23891_/Y (AO211x2_ASAP7_75t_R)
  32.32 3366.82 v frontend/_23915_/Y (OR4x1_ASAP7_75t_R)
  62.99 3429.81 v frontend/_23954_/Y (OR5x2_ASAP7_75t_R)
  41.78 3471.59 ^ frontend/_23955_/Y (NAND2x2_ASAP7_75t_R)
  27.84 3499.43 ^ frontend/_28062_/Y (BUFx6f_ASAP7_75t_R)
  14.77 3514.20 ^ frontend/_30289_/Y (OR3x1_ASAP7_75t_R)
  39.55 3553.75 ^ frontend/_30291_/Y (OA211x2_ASAP7_75t_R)
  55.26 3609.01 v frontend/bpd/_6465_/CON (HAxp5_ASAP7_75t_R)
  20.04 3629.04 ^ frontend/bpd/_2924_/Y (INVx2_ASAP7_75t_R)
  39.53 3668.57 ^ frontend/bpd/_2931_/Y (AND4x2_ASAP7_75t_R)
  22.33 3690.90 ^ frontend/bpd/_2932_/Y (BUFx4f_ASAP7_75t_R)
  10.30 3701.20 v frontend/bpd/_2933_/Y (NAND2x1_ASAP7_75t_R)
  37.56 3738.77 v frontend/bpd/_2934_/Y (XNOR2x2_ASAP7_75t_R)
  45.33 3784.10 v wire8991/Y (BUFx6f_ASAP7_75t_R)
  41.69 3825.78 v wire8990/Y (BUFx16f_ASAP7_75t_R)
  34.52 3860.30 v frontend/bpd/banked_predictors_0/io_f0_pc[9] (ComposedBranchPredictorBank)
        3860.30   data arrival time

1200.00 1200.00   clock clock (rise edge)
1307.09 2507.09   clock network delay (propagated)
  39.90 2547.00   clock reconvergence pessimism
        2547.00 ^ frontend/bpd/banked_predictors_0/clock (ComposedBranchPredictorBank)
  15.13 2562.13   library setup time
        2562.13   data required time
---------------------------------------------------------
        2562.13   data required time
        -3860.30   data arrival time
---------------------------------------------------------
        -1298.17   slack (VIOLATED)


>>> report_checks -to frontend/bpd/banked_predictors_1
Startpoint: frontend/bpd/banked_predictors_1
            (rising edge-triggered flip-flop clocked by clock)
Endpoint: frontend/bpd/banked_predictors_1
          (rising edge-triggered flip-flop clocked by clock)
Path Group: reg2reg
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
1592.70 1592.70   clock network delay (propagated)
   0.00 1592.70 ^ frontend/bpd/banked_predictors_1/clock (ComposedBranchPredictorBank)
1040.30 2633.00 v frontend/bpd/banked_predictors_1/io_resp_f3_2_taken (ComposedBranchPredictorBank)
  30.23 2663.23 v frontend/bpd/_5979_/Y (AO21x2_ASAP7_75t_R)
  19.33 2682.56 v frontend/f3_bpd_resp/_6400_/Y (AND2x2_ASAP7_75t_R)
  28.19 2710.76 v frontend/f3_bpd_resp/_6401_/Y (AO21x2_ASAP7_75t_R)
  32.49 2743.25 v frontend/_16497_/Y (OA21x2_ASAP7_75t_R)
  23.29 2766.54 v frontend/_16498_/Y (AO31x2_ASAP7_75t_R)
  28.48 2795.02 ^ frontend/_16691_/Y (NAND3x2_ASAP7_75t_R)
  48.96 2843.98 ^ frontend/_16692_/Y (AND4x2_ASAP7_75t_R)
  28.79 2872.77 v frontend/_16693_/Y (NAND2x2_ASAP7_75t_R)
  54.22 2926.99 v frontend/_17876_/Y (OR3x1_ASAP7_75t_R)
  20.24 2947.23 v frontend/_17877_/Y (BUFx6f_ASAP7_75t_R)
  51.93 2999.16 v frontend/_17894_/Y (OR4x2_ASAP7_75t_R)
  40.36 3039.52 v frontend/_18202_/Y (AND2x4_ASAP7_75t_R)
  19.82 3059.34 v frontend/_18242_/Y (AO21x1_ASAP7_75t_R)
  22.22 3081.57 v frontend/_18243_/Y (BUFx12_ASAP7_75t_R)
  15.84 3097.41 ^ frontend/_18244_/Y (CKINVDCx9p33_ASAP7_75t_R)
  25.29 3122.70 ^ frontend/_21982_/Y (BUFx10_ASAP7_75t_R)
  42.82 3165.52 v frontend/_23341_/Y (AOI211x1_ASAP7_75t_R)
  52.09 3217.61 ^ frontend/_23342_/Y (AOI22x1_ASAP7_75t_R)
  52.94 3270.55 v frontend/_23882_/Y (XNOR2x2_ASAP7_75t_R)
  43.89 3314.44 v frontend/_23885_/Y (OR4x2_ASAP7_75t_R)
  20.06 3334.50 v frontend/_23891_/Y (AO211x2_ASAP7_75t_R)
  32.32 3366.82 v frontend/_23915_/Y (OR4x1_ASAP7_75t_R)
  62.99 3429.81 v frontend/_23954_/Y (OR5x2_ASAP7_75t_R)
  41.78 3471.59 ^ frontend/_23955_/Y (NAND2x2_ASAP7_75t_R)
  27.84 3499.43 ^ frontend/_28062_/Y (BUFx6f_ASAP7_75t_R)
  14.77 3514.20 ^ frontend/_30289_/Y (OR3x1_ASAP7_75t_R)
  39.55 3553.75 ^ frontend/_30291_/Y (OA211x2_ASAP7_75t_R)
  55.26 3609.01 v frontend/bpd/_6465_/CON (HAxp5_ASAP7_75t_R)
  20.04 3629.04 ^ frontend/bpd/_2924_/Y (INVx2_ASAP7_75t_R)
  39.53 3668.57 ^ frontend/bpd/_2931_/Y (AND4x2_ASAP7_75t_R)
  22.33 3690.90 ^ frontend/bpd/_2932_/Y (BUFx4f_ASAP7_75t_R)
   9.58 3700.49 v frontend/bpd/_3514_/Y (NAND2x1_ASAP7_75t_R)
  37.37 3737.86 v frontend/bpd/_3515_/Y (XNOR2x2_ASAP7_75t_R)
  44.50 3782.35 v wire8979/Y (BUFx6f_ASAP7_75t_R)
  13.49 3795.85 v frontend/bpd/banked_predictors_1/io_f0_pc[9] (ComposedBranchPredictorBank)
        3795.85   data arrival time

1200.00 1200.00   clock clock (rise edge)
1547.19 2747.19   clock network delay (propagated)
  45.50 2792.69   clock reconvergence pessimism
        2792.69 ^ frontend/bpd/banked_predictors_1/clock (ComposedBranchPredictorBank)
  15.13 2807.82   library setup time
        2807.82   data required time
---------------------------------------------------------
        2807.82   data required time
        -3795.85   data arrival time
---------------------------------------------------------
        -988.02   slack (VIOLATED)


>>> report_checks -from frontend/bpd/banked_predictors_1
Startpoint: frontend/bpd/banked_predictors_1
            (rising edge-triggered flip-flop clocked by clock)
Endpoint: frontend/icache/dataArrayB0Way_3_ext
          (rising edge-triggered flip-flop clocked by clock)
Path Group: reg2reg
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
1592.70 1592.70   clock network delay (propagated)
   0.00 1592.70 ^ frontend/bpd/banked_predictors_1/clock (ComposedBranchPredictorBank)
1040.30 2633.00 v frontend/bpd/banked_predictors_1/io_resp_f3_2_taken (ComposedBranchPredictorBank)
  30.23 2663.23 v frontend/bpd/_5979_/Y (AO21x2_ASAP7_75t_R)
  19.33 2682.56 v frontend/f3_bpd_resp/_6400_/Y (AND2x2_ASAP7_75t_R)
  28.19 2710.76 v frontend/f3_bpd_resp/_6401_/Y (AO21x2_ASAP7_75t_R)
  32.49 2743.25 v frontend/_16497_/Y (OA21x2_ASAP7_75t_R)
  23.29 2766.54 v frontend/_16498_/Y (AO31x2_ASAP7_75t_R)
  28.48 2795.02 ^ frontend/_16691_/Y (NAND3x2_ASAP7_75t_R)
  48.96 2843.98 ^ frontend/_16692_/Y (AND4x2_ASAP7_75t_R)
  28.79 2872.77 v frontend/_16693_/Y (NAND2x2_ASAP7_75t_R)
  54.22 2926.99 v frontend/_17876_/Y (OR3x1_ASAP7_75t_R)
  20.24 2947.23 v frontend/_17877_/Y (BUFx6f_ASAP7_75t_R)
  51.93 2999.16 v frontend/_17894_/Y (OR4x2_ASAP7_75t_R)
  40.36 3039.52 v frontend/_18202_/Y (AND2x4_ASAP7_75t_R)
  19.82 3059.34 v frontend/_18242_/Y (AO21x1_ASAP7_75t_R)
  22.22 3081.57 v frontend/_18243_/Y (BUFx12_ASAP7_75t_R)
  15.84 3097.41 ^ frontend/_18244_/Y (CKINVDCx9p33_ASAP7_75t_R)
  25.29 3122.70 ^ frontend/_21982_/Y (BUFx10_ASAP7_75t_R)
  42.82 3165.52 v frontend/_23341_/Y (AOI211x1_ASAP7_75t_R)
  52.09 3217.61 ^ frontend/_23342_/Y (AOI22x1_ASAP7_75t_R)
  52.94 3270.55 v frontend/_23882_/Y (XNOR2x2_ASAP7_75t_R)
  43.89 3314.44 v frontend/_23885_/Y (OR4x2_ASAP7_75t_R)
  20.06 3334.50 v frontend/_23891_/Y (AO211x2_ASAP7_75t_R)
  32.32 3366.82 v frontend/_23915_/Y (OR4x1_ASAP7_75t_R)
  62.99 3429.81 v frontend/_23954_/Y (OR5x2_ASAP7_75t_R)
  43.03 3472.84 v frontend/_25630_/Y (AND2x6_ASAP7_75t_R)
  26.33 3499.18 v frontend/_28622_/Y (AND3x1_ASAP7_75t_R)
  46.38 3545.56 v frontend/_28624_/Y (OR3x4_ASAP7_75t_R)
  23.38 3568.94 v wire9941/Y (BUFx16f_ASAP7_75t_R)
  64.24 3633.18 v wire9940/Y (BUFx16f_ASAP7_75t_R)
  72.19 3705.37 v wire9939/Y (BUFx16f_ASAP7_75t_R)
  63.28 3768.66 v wire9938/Y (BUFx16f_ASAP7_75t_R)
  69.86 3838.51 v wire9937/Y (BUFx16f_ASAP7_75t_R)
  69.55 3908.06 v wire9936/Y (BUFx16f_ASAP7_75t_R)
  75.81 3983.87 v wire9935/Y (BUFx24_ASAP7_75t_R)
  74.67 4058.54 v wire9934/Y (BUFx24_ASAP7_75t_R)
  74.75 4133.29 v wire9933/Y (BUFx24_ASAP7_75t_R)
  76.84 4210.13 v frontend/icache/_6696_/Y (AND2x6_ASAP7_75t_R)
  18.43 4228.56 v max_length9604/Y (BUFx12f_ASAP7_75t_R)
  65.15 4293.71 v wire9603/Y (BUFx16f_ASAP7_75t_R)
  88.53 4382.24 v frontend/icache/_6715_/Y (AO21x2_ASAP7_75t_R)
  24.16 4406.40 v max_length9511/Y (BUFx12f_ASAP7_75t_R)
  62.37 4468.77 v wire9510/Y (BUFx10_ASAP7_75t_R)
  21.43 4490.20 v frontend/icache/dataArrayB0Way_3_ext/RW0_en (dataArrayB_256x64)
        4490.20   data arrival time

1200.00 1200.00   clock clock (rise edge)
1122.16 2322.16   clock network delay (propagated)
  13.66 2335.83   clock reconvergence pessimism
        2335.83 ^ frontend/icache/dataArrayB0Way_3_ext/RW0_clk (dataArrayB_256x64)
 -71.15 2264.68   library setup time
        2264.68   data required time
---------------------------------------------------------
        2264.68   data required time
        -4490.20   data arrival time
---------------------------------------------------------
        -2225.52   slack (VIOLATED)

@oharboe oharboe deleted the branch-predictor-macro branch November 21, 2024 07:12
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