UnversityEducation_MPSIS

Designing a microprocessor based on RISC-V architecture (SystemVerilog / ASM / Vivado 2019.2)

Laboratory work 1. "Adder"

Laboratory work 2. "Arithmetic-logic unit"

Laboratory work 3. "Register file and memory"

Laboratory work 4. "Primitive programmable device"

https://github.com/MPSU/APS/tree/master