Add names for Zbs instructions

ThinkOpenly · Jul 12, 2024 · 456eecb · 456eecb
1 parent e52650d
commit 456eecb
Showing 1 changed file with 8 additions and 0 deletions.
diff --git a/model/riscv_insts_zbs.sail b/model/riscv_insts_zbs.sail
@@ -22,9 +22,13 @@ mapping clause encdec = ZBS_IOP(shamt, rs1, rd, RISCV_BSETI) if extension("Zbs")
   <-> 0b001010 @ shamt @ rs1 @ 0b001 @ rd @ 0b0010011 if extension("Zbs") & (sizeof(xlen) == 64 | shamt[5] == bitzero)
 
 mapping zbs_iop_mnemonic : biop_zbs <-> string = {
+  $[name "Single-Bit Clear (Immediate)"]
   RISCV_BCLRI <-> "bclri",
+  $[name "Single-Bit Extract (Immediate)"]
   RISCV_BEXTI <-> "bexti",
+  $[name "Single-Bit Invert (Immediate)"]
   RISCV_BINVI <-> "binvi",
+  $[name "Single-Bit Set (Immediate)"]
   RISCV_BSETI <-> "bseti"
 }
 
@@ -62,9 +66,13 @@ mapping clause encdec = ZBS_RTYPE(rs2, rs1, rd, RISCV_BSET) if extension("Zbs")
   <-> 0b0010100 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0110011 if extension("Zbs")
 
 mapping zbs_rtype_mnemonic : brop_zbs <-> string = {
+  $[name "Single-Bit Clear (Register)"]
   RISCV_BCLR    <-> "bclr",
+  $[name "Single-Bit Extract (Register)"]
   RISCV_BEXT    <-> "bext",
+  $[name "Single-Bit Invert (Register)"]
   RISCV_BINV    <-> "binv",
+  $[name "Single-Bit Set (Register)"]
   RISCV_BSET    <-> "bset"
 }