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Add pseudoinstructions
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[Draft]

An implementation is proposed for representing pseudoinstructions in Sail.

The realization is similar to instructions, with a few differences:

1. `union clause ast` -> `union clause pseudo`.

1. `mapping clause assembly` -> `mapping clause pseudo_assembly`.

1. `function clause execute` -> `function clause pseudo_execute`:

   This calls the `execute` clauses for the respective base instructions as
   defined for each pseudoinstruction.

1. `mapping clause encdec`: This is undefined for pseudoinstructions because,
   for one thing, some pseudoinstructions map to more than one instruction.
   This is replaced by a new scattered mapping:
   `function clause pseudo_of`: This maps the pseudoinstruction AST to a list
   of the assembly clauses (strings) of the mapped instructions, for example:

   ```
   function clause pseudo_of(LA(rd, imm)) = [|
     assembly(UTYPE(imm[31..12],rd,RISCV_AUIPC)),
     assembly(ITYPE(imm[11..0],reg_name("x0"),rd,RISCV_ADDI))
   |]

   ```

   This is roughly analogous to `function clause assembly`, but instead
   of representing the instruction syntax, it represents the syntax of the
   mapped instructions.
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Linda-Njau authored and ThinkOpenly committed Aug 21, 2024
1 parent 2078d87 commit 55bd267
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2 changes: 2 additions & 0 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,8 @@ SAIL_DEFAULT_INST += riscv_insts_vext_fp_vm.sail
SAIL_DEFAULT_INST += riscv_insts_vext_red.sail
SAIL_DEFAULT_INST += riscv_insts_vext_fp_red.sail

SAIL_DEFAULT_INST += riscv_pseudos.sail

SAIL_SEQ_INST = $(SAIL_DEFAULT_INST) riscv_jalr_seq.sail
SAIL_RMEM_INST = $(SAIL_DEFAULT_INST) riscv_jalr_rmem.sail riscv_insts_rmem.sail

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60 changes: 60 additions & 0 deletions model/riscv_pseudos.sail
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@@ -0,0 +1,60 @@
/*=======================================================================================*/
/* This Sail RISC-V architecture model, comprising all files and */
/* directories except where otherwise noted is subject the BSD */
/* two-clause license in the LICENSE file. */
/* */
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

/* ******************************************* */
/* This file specifies the pseudoinstructions. */

scattered union pseudo

val pseudo_execute : pseudo -> Retired
scattered function pseudo_execute

val pseudo_assembly : pseudo <-> string
scattered mapping pseudo_assembly

val pseudo_of : pseudo -> list(string)
scattered function pseudo_of

/* ******************************************* */
union clause pseudo = LA : (regidx, bits(32))

mapping clause pseudo_assembly = LA(rd, imm)
<-> "la" ^ spc() ^ reg_name(rd) ^sep() ^ hex_bits_32(imm)

function clause pseudo_of(LA(rd, imm)) = [|
assembly(UTYPE(imm[31..12],rd,RISCV_AUIPC)),
assembly(ITYPE(imm[11..0],reg_name("x0"),rd,RISCV_ADDI))
|]

function clause pseudo_execute LA(rd, imm) = {
if execute(UTYPE(imm[31..12],rd,RISCV_AUIPC)) == RETIRE_SUCCESS &
execute(ITYPE(imm[11..0],reg_name("x0"),rd,RISCV_ADDI)) == RETIRE_SUCCESS then
RETIRE_SUCCESS
else
RETIRE_FAIL
}

/* ******************************************* */
union clause pseudo = VNEG : (regidx, regidx)

mapping clause pseudo_assembly = VNEG(vs, vd)
<-> "vneg.v" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs)

function clause pseudo_of(VNEG(vs, vd)) = [|
assembly(VXTYPE(VX_VRSUB, 0b1, vs, reg_name("x0"), vd))
|]

function clause pseudo_execute VNEG(vs, vd) =
execute(VXTYPE(VX_VRSUB, 0b1, vs, 0b00000, vd))

/* ******************************************* */

end pseudo_of
end pseudo_assembly
end pseudo_execute
end pseudo

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