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Sail rebase now requires quoted strings in annotations
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@ThinkOpenly
ThinkOpenly committed Jun 17, 2024
1 parent acef250 commit 9e0a892
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Showing 2 changed files with 36 additions and 36 deletions.
44 changes: 22 additions & 22 deletions model/riscv_insts_base.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ mapping clause assembly = RISCV_JAL(imm, rd)
<-> "jal" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_signed_21(imm)

/* ****************************************************************** */
$[name jump and link register]
$[name "jump and link register"]
/*!
* The target address is obtained by adding the sign-extended 12-bit
* I-immediate to the register rs1, then setting the
Expand All @@ -107,7 +107,7 @@ mapping clause assembly = RISCV_JALR(imm, rs1, rd)
/* see riscv_jalr_seq.sail or riscv_jalr_rmem.sail for the execute clause. */

/* ****************************************************************** */
$[name conditional branch]
$[name "conditional branch"]
/*!
* The target address for this branch instruction is determined by combining
* the sign-extended 13-bit immediate value with the contents of register rs1.
Expand Down Expand Up @@ -230,25 +230,25 @@ function clause execute (ITYPE (imm, rs1, rd, op)) = {
}

mapping itype_mnemonic : iop <-> string = {
$[name add immediate]
$[name "add immediate"]
RISCV_ADDI <-> "addi",
$[name set less than immediate]
$[name "set less than immediate"]
RISCV_SLTI <-> "slti",
$[name set less than immediate unsigned]
$[name "set less than immediate unsigned"]
RISCV_SLTIU <-> "sltiu",
$[name XOR immediate]
$[name "XOR immediate"]
RISCV_XORI <-> "xori",
$[name OR immediate]
$[name "OR immediate"]
RISCV_ORI <-> "ori",
$[name AND immediate]
$[name "AND immediate"]
RISCV_ANDI <-> "andi"
}

mapping clause assembly = ITYPE(imm, rs1, rd, op)
<-> itype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_signed_12(imm)

/* ****************************************************************** */
$[name Shift Immediate]
$[name "Shift Immediate"]
/*!
* The SHIFTIOP (Shift Immediate Operation) instruction format is used for
* operations that involve shifting the bits of a register by an immediate
Expand Down Expand Up @@ -365,7 +365,7 @@ mapping clause assembly = RTYPE(rs2, rs1, rd, op)
<-> rtype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)

/* ****************************************************************** */
$[name Load]
$[name "Load"]
/*!
* The LOAD instruction format is used for loading data from memory into a
* register. The specific operation is determined by the word width (size),
Expand Down Expand Up @@ -445,7 +445,7 @@ mapping clause assembly = LOAD(imm, rs1, rd, is_unsigned, size, aq, rl)
<-> "l" ^ size_mnemonic(size) ^ maybe_u(is_unsigned) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_signed_12(imm) ^ "(" ^ reg_name(rs1) ^ ")"

/* ****************************************************************** */
$[name Store]
$[name "Store"]
/*!
* The STORE instruction format is used for storing data from a register into
* memory. The specific operation is determined by the word width (size) and
Expand Down Expand Up @@ -498,7 +498,7 @@ mapping clause assembly = STORE(imm, rs2, rs1, size, aq, rl)
<-> "s" ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_signed_12(imm) ^ opt_spc() ^ "(" ^ opt_spc() ^ reg_name(rs1) ^ opt_spc() ^ ")"

/* ****************************************************************** */
$[name Add Immediate Word]
$[name "Add Immediate Word"]
/*!
* The ADDIW instruction involves adding a sign-extended
* 12-bit immediate value to the content of register rs1. The result is a 32-bit
Expand Down Expand Up @@ -589,7 +589,7 @@ mapping clause assembly = RTYPEW(rs2, rs1, rd, op)
if sizeof(xlen) == 64

/* ****************************************************************** */
$[name Shift Immediate Word]
$[name "Shift Immediate Word"]
/*!
* The SHIFTIWOP instruction set deals with
* immediate shift operations on 32-bit values, with the result sign-extended
Expand Down Expand Up @@ -637,7 +637,7 @@ mapping clause assembly = SHIFTIWOP(shamt, rs1, rd, op)
if sizeof(xlen) == 64

/* ****************************************************************** */
$[name Fence (Memory)]
$[name "Fence (Memory)"]
/*!
* The FENCE instruction is used to provide memory ordering guarantees.
* It specifies ordering constraints on memory operations that precede
Expand Down Expand Up @@ -723,7 +723,7 @@ mapping clause assembly = FENCE(pred, succ)
<-> "fence" ^ spc() ^ fence_bits(pred) ^ sep() ^ fence_bits(succ)

/* ****************************************************************** */
$[name Fence (Total Store Order)]
$[name "Fence (Total Store Order)"]
/*!
* The FENCE_TSO instruction is a memory
* ordering instruction that provides a stronger memory consistency model
Expand Down Expand Up @@ -754,7 +754,7 @@ mapping clause assembly = FENCE_TSO(pred, succ)
<-> "fence.tso" ^ spc() ^ fence_bits(pred) ^ sep() ^ fence_bits(succ)

/* ****************************************************************** */
$[name Fence (Instruction)]
$[name "Fence (Instruction)"]
/*!
* The FENCEI instruction is a memory ordering instruction that
* provides a barrier to the instruction stream.
Expand All @@ -773,7 +773,7 @@ function clause execute FENCEI() = { /* __barrier(Barrier_RISCV_i); */ RETIRE_SU
mapping clause assembly = FENCEI() <-> "fence.i"

/* ****************************************************************** */
$[name Environment Call]
$[name "Environment Call"]
/*!
* The ECALL instruction, previously called SCALL is used to make a
* request to the supporting execution environment, typically an
Expand Down Expand Up @@ -802,7 +802,7 @@ function clause execute ECALL() = {
mapping clause assembly = ECALL() <-> "ecall"

/* ****************************************************************** */
$[name Machine-level Return]
$[name "Machine-level Return"]
/*!
* The MRET instruction is used to return from a machine-level exception,
* transferring control back to the instruction following the one that
Expand All @@ -827,7 +827,7 @@ function clause execute MRET() = {
mapping clause assembly = MRET() <-> "mret"

/* ****************************************************************** */
$[name Supervisor-level Return]
$[name "Supervisor-level Return"]
/*!
* The SRET instruction is used to return from a supervisor-level exception,
* transferring control back to the instruction following the one that
Expand Down Expand Up @@ -857,7 +857,7 @@ function clause execute SRET() = {
mapping clause assembly = SRET() <-> "sret"

/* ****************************************************************** */
$[name Environment Breakpoint]
$[name "Environment Breakpoint"]
/*!
* The EBREAK instruction, previously called SBREAK is utilized by
* debuggers to trigger a breakpoint exception, leading to a transfer
Expand All @@ -877,7 +877,7 @@ function clause execute EBREAK() = {
mapping clause assembly = EBREAK() <-> "ebreak"

/* ****************************************************************** */
$[name Wait For Interrupt]
$[name "Wait For Interrupt"]
/*!
* The WFI (Wait For Interrupt) instruction is used to suspend the execution
* pipeline until an interrupt or an event occurs. Its behavior depends on the
Expand Down Expand Up @@ -905,7 +905,7 @@ function clause execute WFI() =
mapping clause assembly = WFI() <-> "wfi"

/* ****************************************************************** */
$[name Store Fence (Virtual Memory Address)]
$[name "Store Fence (Virtual Memory Address)"]
/*!
* The SFENCE.VMA instruction is used to synchronize the store queue and flush
* TLB entries based on virtual memory address and optional ASID values.
Expand Down
28 changes: 14 additions & 14 deletions model/riscv_insts_zkn.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,13 +11,13 @@
* ----------------------------------------------------------------------
*/

$[name SHA2-256 Sigma0]
$[name "SHA2-256 Sigma0"]
union clause ast = SHA256SIG0 : (regidx, regidx)
$[name SHA2-256 Sigma1]
$[name "SHA2-256 Sigma1"]
union clause ast = SHA256SIG1 : (regidx, regidx)
$[name SHA2-256 Sum0]
$[name "SHA2-256 Sum0"]
union clause ast = SHA256SUM0 : (regidx, regidx)
$[name SHA2-256 Sum1]
$[name "SHA2-256 Sum1"]
union clause ast = SHA256SUM1 : (regidx, regidx)

mapping clause encdec = SHA256SUM0 (rs1, rd) if extension("Zknh")
Expand Down Expand Up @@ -157,17 +157,17 @@ function clause execute (AES32DSI (bs, rs2, rs1, rd)) = {
* ----------------------------------------------------------------------
*/

$[name SHA2-512 Sigma0 low]
$[name "SHA2-512 Sigma0 low"]
union clause ast = SHA512SIG0L : (regidx, regidx, regidx)
$[name SHA2-512 Sigma0 high]
$[name "SHA2-512 Sigma0 high"]
union clause ast = SHA512SIG0H : (regidx, regidx, regidx)
$[name SHA2-512 Sigma1 low]
$[name "SHA2-512 Sigma1 low"]
union clause ast = SHA512SIG1L : (regidx, regidx, regidx)
$[name SHA2-512 Sigma1 high]
$[name "SHA2-512 Sigma1 high"]
union clause ast = SHA512SIG1H : (regidx, regidx, regidx)
$[name SHA2-512 Sum0 (RV32)]
$[name "SHA2-512 Sum0 (RV32)"]
union clause ast = SHA512SUM0R : (regidx, regidx, regidx)
$[name SHA2-512 Sum1 (RV32)]
$[name "SHA2-512 Sum1 (RV32)"]
union clause ast = SHA512SUM1R : (regidx, regidx, regidx)

mapping clause encdec = SHA512SUM0R (rs2, rs1, rd) if extension("Zknh") & sizeof(xlen) == 32
Expand Down Expand Up @@ -365,13 +365,13 @@ function clause execute (AES64DS(rs2, rs1, rd)) = {
* ----------------------------------------------------------------------
*/

$[name SHA2-512 Sigma0]
$[name "SHA2-512 Sigma0"]
union clause ast = SHA512SIG0 : (regidx, regidx)
$[name SHA2-512 Sigma1]
$[name "SHA2-512 Sigma1"]
union clause ast = SHA512SIG1 : (regidx, regidx)
$[name SHA2-512 Sum0 (RV64)]
$[name "SHA2-512 Sum0 (RV64)"]
union clause ast = SHA512SUM0 : (regidx, regidx)
$[name SHA2-512 Sum1 (RV64)]
$[name "SHA2-512 Sum1 (RV64)"]
union clause ast = SHA512SUM1 : (regidx, regidx)

mapping clause encdec = SHA512SUM0 (rs1, rd) if extension("Zknh") & sizeof(xlen) == 64
Expand Down

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