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1. VHDL_Ident-Player VHDL_Ident-Player Public

   As part of my final thesis, an Ident Loop Player based on an FPGA is being developed

   Verilog 1

2. Task_Mgmt_exercise Task_Mgmt_exercise Public

   C

3. Alarm_Clock_Task Alarm_Clock_Task Public

   C

4. U_PiCalc_HS2023 U_PiCalc_HS2023 Public

   Forked from Juventus-Technikerschule-HF/U_PiCalc_HS2023_Template

   C

5. Deadlock_Test_HS2023_HW Deadlock_Test_HS2023_HW Public

   Forked from Juventus-Technikerschule-HF/Deadlock_Test_HS2023

   C

6. RaceConditionX_HS2023_HW RaceConditionX_HS2023_HW Public

   Forked from Juventus-Technikerschule-HF/RaceConditionX_HS2023

   C