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IR Changes #188
IR Changes #188
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…ave default parameter values, make Register take an Int as parameter instead of BitVecType, split Memory into StackMemory and SharedMemory, rename LocalAssign to Assign to avoid confusion about what 'local' means in this context
Thinking about it a little further, Memory probably shouldn't be an Expr either |
These were generally relics of the IR hewing closely to BAP and/or Boogie for convenience |
The state register flags (ZF, NF, etc.) should probably be treated as globals and not locals because it probably isn't impossible the state of them in one procedure is relevant for the state in another procedure due to compiler optimisations? |
This is a good start, some further ideas:
I agree I think this makes sense |
I am not sure how you make these types more concrete. If these do not match, obviously invalid Boogie is generated which is why I have not yet bothered to implement type checking for these sizes. That could still be done but it's hardly a priority.
If a MemoryAssign is a write to shared state, then its mem parameter will be a SharedMemory. Which analysis is all this important for?
This sounds needlessly convoluted for no real benefit. |
# Conflicts: # src/main/scala/analysis/Analysis.scala # src/main/scala/analysis/SteensgaardAnalysis.scala # src/main/scala/ir/Statement.scala # src/main/scala/ir/Visitor.scala # src/main/scala/util/RunUtils.scala
# Conflicts: # src/test/scala/LiveVarsAnalysisTests.scala # src/test/scala/PointsToTest.scala # src/test/scala/ir/IRTest.scala
This is ready to merge @ailrst |
# Conflicts: # src/main/scala/translating/GTIRBToIR.scala # src/main/scala/translating/SemanticsLoader.scala
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I think this change is good you can ignore my comments if you want.
private val framePointer = Register("R29", BitVecType(64)) | ||
private val stackPointer = Register("R31", 64) | ||
private val linkRegister = Register("R30", 64) | ||
private val framePointer = Register("R29", 64) |
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I don't think this change is worth it, it might cause problems if we want to change back to integers e.g. if we are interested in something like the SMACK int selection with cegar paper. Trying to make register an alias for global bitvector variable using inheritance is a bit too tricky imo. It seems cleaner to me to only have regular variables where scope is a parameter/field rather than a trait mixin. We could approach variables being shared similarly, but I do think it makes sense to have shared and unshared be type-incompatible. E.g.
enum VariableKind(name, type, scope, shared):
case Memory(n,keytype,valtype) extends Variable(n,MapType(keytype,valtype), Global, Shared)
case Variable(n,t, scope) extends Variable(n,t, scope, Unshared)
case Register(n, sz) extends Variable(n, BitVecType(sz), Global, Unsharedl)
(as implemented as a trait/case class heirachy this just means moving name,type,scope,shared to the parent trait's constructor?)
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This PR doesn't make any changes to the scope. If you want to propose changes to how the scope works, you can do that separately. What you're suggesting would make the type system weaker though. What this PR does change is make it so Memory is not an Expr, and so (correctly) is no longer allowed to appear arbitrarily inside other Exprs.
I did consider the implications for supporting an integer representation (as in SMACK) but that would require wider changes anyway, as everything else already assumes everything is bitvectors - the Memory case class already does for instance.
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Yeah I agree, if we want to lift registers to variables then we can lift registers to variables.
case localAssign: LocalAssign => | ||
m = m.diff(localAssign.rhs.variables) | ||
if ignoreRegions.contains(localAssign.lhs) then m else m + localAssign.lhs | ||
case assign: Assign => |
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I am still in favour of having a separate load instruction so that assign is clearly pure computation, but its not essential.
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As we've discussed before. this means creating a new temporary variable for nearly every load, adding a lot of bloat to the IR without actually improving anything.
# Conflicts: # src/main/scala/analysis/Analysis.scala # src/main/scala/analysis/InterprocSteensgaardAnalysis.scala # src/main/scala/analysis/RegToMemAnalysis.scala # src/main/scala/analysis/SSAForm.scala
This is partially in response to discussions regarding #185 and #184 and does the following: