Run cargo fmt after rustup to 1.72.0

VHDL-LS · Sep 8, 2023 · 184a589 · 184a589
1 parent 5137bef
commit 184a589
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Showing 3 changed files with 10 additions and 4 deletions.
diff --git a/vhdl_lang/src/analysis/root.rs b/vhdl_lang/src/analysis/root.rs
@@ -960,7 +960,9 @@ impl DesignRoot {
                 let std_logic_arena = &data.result().arena;
                 if let AnyDesignUnit::Primary(primary) = data.deref() {
                     if let Some(ent) = primary.ent_id() {
-                        let AnyEntKind::Design(Design::Package(_, ref region)) = std_logic_arena.get(ent).kind() else {
+                        let AnyEntKind::Design(Design::Package(_, ref region)) =
+                            std_logic_arena.get(ent).kind()
+                        else {
                             unreachable!()
                         };
 

diff --git a/vhdl_lang/src/analysis/standard.rs b/vhdl_lang/src/analysis/standard.rs
@@ -757,7 +757,10 @@ impl<'a> AnalyzeContext<'a> {
         typ: TypeEnt<'a>,
         matching_op: bool,
     ) -> impl Iterator<Item = EntRef<'a>> {
-        let Type::Array{indexes, elem_type, ..}  = typ.kind() else {
+        let Type::Array {
+            indexes, elem_type, ..
+        } = typ.kind()
+        else {
             unreachable!("Must be array type")
         };
 

diff --git a/vhdl_lang/src/syntax/expression.rs b/vhdl_lang/src/syntax/expression.rs
@@ -332,8 +332,9 @@ fn parse_expression_or_aggregate(stream: &TokenStream) -> ParseResult<WithPos<Ex
     {
         let WithPos {
             item: Choice::Expression(expr),
-            pos
-        } = choices.pop().unwrap() else {
+            pos,
+        } = choices.pop().unwrap()
+        else {
             unreachable!();
         };