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Selected names from 'unusual' places #249

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Schottkyc137 opened this issue Jan 7, 2024 · 1 comment
Open

Selected names from 'unusual' places #249

Schottkyc137 opened this issue Jan 7, 2024 · 1 comment
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@Schottkyc137
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Schottkyc137 commented Jan 7, 2024

VHDL allows to prefix a name with the label of the enclosing element as 'scope'. For example, for processes:

P: process
    variable DATA: INTEGER;
begin
    -- Within process P, the name "P.DATA" denotes a named entity
    -- declared in process P.
end process;

This example is directly taken from the LRM (8.3; examples)

At the moment, the language server sees this as an error.

The same is likely true for blocks, generate statements and probably more.

@lgu-appear
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I didn't even know this existed in VHDL, but I find it amazing to help readability in code when you have for..generate and block. Would be cool to see this fixed!

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