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Simple VHDL2019 constructs #288

Merged

Schottkyc137 merged 2 commits into VHDL-LS:master from Schottkyc137:vhdl2019-simple

Apr 14, 2024

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Schottkyc137 commented Apr 14, 2024

parse constructs that are easy to support

Allow trailing semicolons on interface lists
second component keyword is optional for component declarations

Schottkyc137 added 2 commits

April 14, 2024 17:12


          Make final component keyword optional for VHDL2019

45e7ea7


          Allow trailing semicolons for interface lists for VHDL >= 2019

f878894

Schottkyc137 merged commit 3d1db16 into VHDL-LS:master

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