Fix RISC-V JALR lift when rs1==rd #6213
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The lifting change is good, however will require changes to the function recognizer, see the second pair of images. Before: Before: |
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I went ahead and added the required changes, thank you for the PR! Also thank you to @jeanmicheldeva, apologies that your PR wasn't merged, I am going to try and get your other changed merged shortly. Relevant PR: #6064 |
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When the source and destination register are the same, the current implementation of lifting for
jalrin RISC-V results in the jump target being overwritten by the return address. This PR avoids the issue by copying the jump target to a LLIL temporary register before writing the destination register.This situation comes up in certain binaries when LLVM optimizes for size and performs compiler outlining of register stack spills. The attached zipfile contains a build of a rust RISC-V Embassy project that demonstrates the issue in a function at 0x00000b08.
riscv-jalr-issue.zip