Initial loongarch port

Co-authored-by: yangwenqing <[email protected]> Signed-off-by: Leslie Zhai <[email protected]> Signed-off-by: yangwenqing <[email protected]>
VectorCamp · Oct 11, 2023 · 2277a93 · 2277a93
1 parent aa8af26
commit 2277a93
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diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required (VERSION 3.18.4)
+cmake_minimum_required (VERSION 3.13.4)
 
 project (vectorscan C CXX)
 
@@ -127,6 +127,9 @@ elseif (ARCH_ARM32 OR ARCH_AARCH64)
 elseif (ARCH_PPC64EL)
     include (${CMAKE_MODULE_PATH}/cflags-ppc64le.cmake)
     set(ARCH_FLAG mcpu)
+elseif (ARCH_LOONGARCH64)
+    include (${CMAKE_MODULE_PATH}/cflags-loongarch64.cmake)
+    set(ARCH_FLAG march)
 endif ()
 
 # Detect Native arch flags if requested
@@ -152,6 +155,11 @@ foreach (CONFIG ${CMAKE_BUILD_TYPE} ${CMAKE_CONFIGURATION_TYPES})
     string(REGEX REPLACE "-O[^ ]*" "" CMAKE_CXX_FLAGS_${CONFIG} "${CMAKE_CXX_FLAGS_${CONFIG}}")
 endforeach ()
 
+if (ARCH_LOONGARCH64)
+    set(ARCH_C_FLAGS "-mlsx")
+    set(ARCH_CXX_FLAGS "-mlsx")
+endif(ARCH_LOONGARCH64)
+
 message(STATUS "ARCH_C_FLAGS   : ${ARCH_C_FLAGS}")
 message(STATUS "ARCH_CXX_FLAGS : ${ARCH_CXX_FLAGS}")
 
@@ -178,7 +186,7 @@ set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${ARCH_CXX_FLAGS}")
 # PCRE check, we have a fixed requirement for PCRE to use Chimera
 # and hscollider
 set(PCRE_REQUIRED_MAJOR_VERSION 8)
-set(PCRE_REQUIRED_MINOR_VERSION 41)
+set(PCRE_REQUIRED_MINOR_VERSION 39)
 set(PCRE_REQUIRED_VERSION ${PCRE_REQUIRED_MAJOR_VERSION}.${PCRE_REQUIRED_MINOR_VERSION})
 include (${CMAKE_MODULE_PATH}/pcre.cmake)
 if (NOT CORRECT_PCRE_VERSION)
@@ -252,6 +260,11 @@ elseif (ARCH_PPC64EL)
 set (hs_exec_common_SRCS
     ${hs_exec_common_SRCS}
     src/util/arch/ppc64el/cpuid_flags.c)
+elseif (ARCH_LOONGARCH64)
+set (hs_exec_common_SRCS
+    ${hs_exec_common_SRCS}
+    src/util/arch/loongarch64/cpuid_flags.c
+    )
 endif ()
 
 set (hs_exec_SRCS
@@ -410,6 +423,11 @@ set (hs_exec_SRCS
     ${hs_exec_SRCS}
     src/nfa/vermicelli_simd.cpp
     src/util/supervector/arch/ppc64el/impl.cpp)
+elseif (ARCH_LOONGARCH64)
+set (hs_exec_SRCS
+    ${hs_exec_SRCS}
+    src/nfa/vermicelli_simd.cpp
+    src/util/supervector/arch/loongarch64/impl.cpp)
 endif()
 
 if (ARCH_IA32 OR ARCH_X86_64)

diff --git a/README.md b/README.md
@@ -1,9 +1,9 @@
 # Vectorscan?
 
 A fork of Intel's Hyperscan, modified to run on more platforms. Currently ARM NEON/ASIMD
-is 100% functional, and Power VSX are in development. ARM SVE2 will be implemented when
-harwdare becomes accessible to the developers. More platforms will follow in the future,
-on demand/request.
+is 100% functional, LoongArch LSX is 100% functional, and Power VSX are in development.
+ARM SVE2 will be implemented when harwdare becomes accessible to the developers.
+More platforms will follow in the future, on demand/request.
 
 Vectorscan will follow Intel's API and internal algorithms where possible, but will not
 hesitate to make code changes where it is thought of giving better performance or better

diff --git a/cmake/archdetect.cmake b/cmake/archdetect.cmake
@@ -84,6 +84,9 @@ else()
     elseif(ARCH_ARM32)
        set(GNUCC_ARCH armv7a)
        set(TUNE_FLAG generic)
+    elseif(ARCH_LOONGARCH64)
+       set(GNUCC_ARCH la464)
+       set(TUNE_FLAG generic)
     else()
        set(GNUCC_ARCH power9)
        set(TUNE_FLAG power9)

diff --git a/cmake/cflags-loongarch64.cmake b/cmake/cflags-loongarch64.cmake
@@ -0,0 +1,19 @@
+
+CHECK_INCLUDE_FILE_CXX(lsxintrin.h HAVE_C_LOONGARCH64_LSXINTRIN_H)
+
+if (HAVE_C_LOONGARCH64_LSXINTRIN_H)
+    set (INTRIN_INC_H "lsxintrin.h")
+else()
+    message (FATAL_ERROR "No intrinsics header found for LSX")
+endif ()
+
+set(CMAKE_REQUIRED_FLAGS "-mlsx")
+CHECK_C_SOURCE_COMPILES("#include <${INTRIN_INC_H}>
+int main() {
+    __m128i a = __lsx_vreplgr2vr_w(1);
+    (void)a;
+}" HAVE_LSX)
+
+if (NOT HAVE_LSX)
+    message(FATAL_ERROR "LSX support required for LoongArch support")
+endif ()
diff --git a/cmake/config.h.in b/cmake/config.h.in
@@ -24,6 +24,9 @@
 /* "Define if building for PPC64EL" */
 #cmakedefine ARCH_PPC64EL
 
+/* "Define if building for LOONGARCH64" */
+#cmakedefine ARCH_LOONGARCH64
+
 /* "Define if cross compiling for AARCH64" */
 #cmakedefine CROSS_COMPILE_AARCH64
 
@@ -81,6 +84,9 @@
 /* C compiler has arm_neon.h */
 #cmakedefine HAVE_C_PPC64EL_ALTIVEC_H
 
+/* C compiler has lsxintrin.h */
+#cmakedefine HAVE_C_LOONGARCH64_LSXINTRIN_H
+
 /* Define to 1 if you have the declaration of `pthread_setaffinity_np', and to
    0 if you don't. */
 #cmakedefine HAVE_DECL_PTHREAD_SETAFFINITY_NP

diff --git a/cmake/platform.cmake b/cmake/platform.cmake
@@ -5,7 +5,8 @@ CHECK_C_SOURCE_COMPILES("#if !(defined(__i386__) || defined(_M_IX86))\n#error no
 CHECK_C_SOURCE_COMPILES("#if !defined(__ARM_ARCH_ISA_A64)\n#error not 64bit\n#endif\nint main(void) { return 0; }" ARCH_AARCH64)
 CHECK_C_SOURCE_COMPILES("#if !defined(__ARM_ARCH_ISA_ARM)\n#error not 32bit\n#endif\nint main(void) { return 0; }" ARCH_ARM32)
 CHECK_C_SOURCE_COMPILES("#if !defined(__PPC64__) && !(defined(__LITTLE_ENDIAN__) && defined(__VSX__))\n#error not ppc64el\n#endif\nint main(void) { return 0; }" ARCH_PPC64EL)
-if (ARCH_X86_64 OR ARCH_AARCH64 OR ARCH_PPC64EL)
+CHECK_C_SOURCE_COMPILES("#if !(defined(__loongarch_lp64) || defined( __loongarch64))\n#error not 64bit\n#endif\nint main(void) { return 0; }" ARCH_LOONGARCH64)
+if (ARCH_X86_64 OR ARCH_AARCH64 OR ARCH_PPC64EL OR ARCH_LOONGARCH64)
   set(ARCH_64_BIT TRUE)
 else()
   set(ARCH_32_BIT TRUE)

diff --git a/src/hs.cpp b/src/hs.cpp
@@ -48,6 +48,7 @@
 #if defined(ARCH_IA32) || defined(ARCH_X86_64)
 #include "util/arch/x86/cpuid_inline.h"
 #elif defined(ARCH_ARM32) || defined(ARCH_AARCH64)
+#elif defined(ARCH_LOONGARCH64)
 #endif
 #include "util/depth.h"
 #include "util/popcount.h"

diff --git a/src/hs_valid_platform.c b/src/hs_valid_platform.c
@@ -52,5 +52,7 @@ hs_error_t HS_CDECL hs_valid_platform(void) {
     }
 #elif defined(ARCH_PPC64EL)
     return HS_SUCCESS;    
+#elif defined(ARCH_LOONGARCH64)
+    return HS_SUCCESS;    
 #endif
 }
diff --git a/src/nfa/loongarch64/shufti.hpp b/src/nfa/loongarch64/shufti.hpp
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2015-2017, Intel Corporation
+ * Copyright (c) 2020-2021, VectorCamp PC
+ * Copyright (c) 2023, Loongson Technology
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of Intel Corporation nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** \file
+ * \brief Shufti: character class acceleration.
+ */
+
+template <uint16_t S>
+static really_inline
+const SuperVector<S> blockSingleMask(SuperVector<S> mask_lo, SuperVector<S> mask_hi, SuperVector<S> chars) {
+    const SuperVector<S> low4bits = SuperVector<S>::dup_u8(0xf);
+
+    SuperVector<S> c_lo = chars & low4bits;
+    SuperVector<S> c_hi = chars.template vshr_8_imm<4>();
+    c_lo = mask_lo.template pshufb<false>(c_lo);
+    c_hi = mask_hi.template pshufb<false>(c_hi);
+
+    return (c_lo & c_hi) > (SuperVector<S>::Zeroes());
+}
+
+template <uint16_t S>
+static really_inline
+SuperVector<S> blockDoubleMask(SuperVector<S> mask1_lo, SuperVector<S> mask1_hi, SuperVector<S> mask2_lo, SuperVector<S> mask2_hi, SuperVector<S> chars) {
+
+    const SuperVector<S> low4bits = SuperVector<S>::dup_u8(0xf);
+    SuperVector<S> chars_lo = chars & low4bits;
+    chars_lo.print8("chars_lo");
+    SuperVector<S> chars_hi = chars.template vshr_64_imm<4>() & low4bits;
+    chars_hi.print8("chars_hi");
+    SuperVector<S> c1_lo = mask1_lo.template pshufb<true>(chars_lo);
+    c1_lo.print8("c1_lo");
+    SuperVector<S> c1_hi = mask1_hi.template pshufb<true>(chars_hi);
+    c1_hi.print8("c1_hi");
+    SuperVector<S> t1 = c1_lo | c1_hi;
+    t1.print8("t1");
+
+    SuperVector<S> c2_lo = mask2_lo.template pshufb<true>(chars_lo);
+    c2_lo.print8("c2_lo");
+    SuperVector<S> c2_hi = mask2_hi.template pshufb<true>(chars_hi);
+    c2_hi.print8("c2_hi");
+    SuperVector<S> t2 = c2_lo | c2_hi;
+    t2.print8("t2");
+    t2.template vshr_128_imm<1>().print8("t2.vshr_128(1)");
+    SuperVector<S> t = t1 | (t2.template vshr_128_imm<1>());
+    t.print8("t");
+
+    return !t.eq(SuperVector<S>::Ones());
+}
diff --git a/src/nfa/loongarch64/truffle.hpp b/src/nfa/loongarch64/truffle.hpp
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2015-2017, Intel Corporation
+ * Copyright (c) 2020-2021, VectorCamp PC
+ * Copyright (c) 2023, Loongson Technology
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of Intel Corporation nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** \file
+ * \brief Truffle: character class acceleration.
+ *
+ */
+
+template <uint16_t S>
+static really_inline
+const SuperVector<S> blockSingleMask(SuperVector<S> shuf_mask_lo_highclear, SuperVector<S> shuf_mask_lo_highset, SuperVector<S> chars) {
+
+    chars.print8("chars");
+    shuf_mask_lo_highclear.print8("shuf_mask_lo_highclear");
+    shuf_mask_lo_highset.print8("shuf_mask_lo_highset");
+
+    SuperVector<S> highconst = SuperVector<S>::dup_u8(0x80);
+    highconst.print8("highconst");
+    SuperVector<S> shuf_mask_hi = SuperVector<S>::dup_u64(0x8040201008040201);
+    shuf_mask_hi.print8("shuf_mask_hi");
+
+    SuperVector<S> shuf1 = shuf_mask_lo_highclear.pshufb(chars);
+    shuf1.print8("shuf1");
+    SuperVector<S> t1 = chars ^ highconst;
+    t1.print8("t1");
+    SuperVector<S> shuf2 = shuf_mask_lo_highset.pshufb(t1);
+    shuf2.print8("shuf2");
+    SuperVector<S> t2 = highconst.opandnot(chars.template vshr_64_imm<4>());
+    t2.print8("t2");
+    SuperVector<S> shuf3 = shuf_mask_hi.pshufb(t2);
+    shuf3.print8("shuf3");
+    SuperVector<S> res = (shuf1 | shuf2) & shuf3;
+    res.print8("(shuf1 | shuf2) & shuf3");
+
+    return !res.eq(SuperVector<S>::Zeroes());
+}