# 100 days of RTL Design using Verilog
Welcome to the 100 Days of RTL (Register Transfer Level) Design Challenge! This challenge is designed 
to help you improve your skills in digital circuit design using Verilog, a hardware description 
language widely used in the industry.

What is verilog: 
	Verilog is a hardware description language used for modeling electronic systems. It allows 
 designersto describe digital circuits at various levels of abstraction.Verilog facilitates 
 simulation, synthesis, andverification of digital designs.It supports both behavioral and structural 
 modeling paradigms. Widelyutilized in ASIC and FPGA design, Verilog enables efficient hardware 
 development. A comprehensive series of RTL design tutorials covering various aspects of digital 
 design

What is RTL Design?
	RTL Design involves describing digital circuits at a low level of abstraction, focusing on the 
 flow of data between registers.It's a crucial step in hardware development, especially for ASIC 
 and FPGA designs.