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When synthesizing DSWG instances with the latest
dev
Vivado raises the following error:This is due to a variable in the generated SystemVerilog code
The fix is to use the corresponding enum values (e.g.
STATE_LOOP_SIMD
instead of1
). However, changing this in the codegen breaks the non-dynamic SWG since it uses the same value as a constructor parameter, so fixing that in turn requires moving the definition of the enum to the global scope. To avoid errors due to possible multiple definitions, I've addedifdef
guards around it.Note that the error was previously not detected because the DSWG unit tests do not include any synthesis. This PR adds synthesis to one of the DSWG testcases to detect future occurances of the issue.