[AIE2] Fix missing VST.SRS combine

[abhinay-anubola]

Combined into VST.SRS, if two 256-bit SRS are input to 512-bit STORE through CONCAT

[martien-de-jong]

I'm wondering whether we would want to normalize this to G_CONCAT_VECTORS. Any way, having common pattern recognizer classes for these common glue patterns (e.g. CONCAT(vsz, vsz) -> vszx2) would really help readability, and be good candidates to have tablegen support for pattern matching.

[andcarminati]

I agree, if we can solve this in PostLegalizer combiner I think the solution can be simpler. Something like:

X = CONCAT(SRS(A), SRS(B))

To something like:

X = SRS2(CONCAT(A, B))

And let Selector intact.

[gbossu]

That indeed seems to be a better way, but I'd rather not split the target-specific handling of intrinsics in one more place, and keep it solely here. I think we all agree the logic for selecting opcodes in this file isn't great, but hopefully we can table-gen-erate most of the logic at some point. Hopefully :)

[andcarminati]

Hi @abhinay-anubola,

I feel that we need to think in a common approach here. I identified similar case in DivAttributeBroadcasting_aie2_bf16_0:

    %198:vregbank(<16 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aie2.v16accfloat.to.v16bf16), %197(<8 x s64>)
    %199:accregbank(<8 x s64>) = G_INTRINSIC intrinsic(@llvm.aie2.ext.512.1024.acc), %196(<16 x s64>), %74(s32)
    %200:vregbank(<16 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aie2.v16accfloat.to.v16bf16), %199(<8 x s64>)
    %201:vregbank(<32 x s16>) = G_INTRINSIC intrinsic(@llvm.aie2.concat.bf512.bf256), %198(<16 x s16>), %200(<16 x s16>)
    %224:modregbank(s20) = G_CONSTANT i20 64
    %202:ptrregbank(p0) = G_AIE_POSTINC_STORE %138(<32 x s16>), %38, %224(s20) :: (store (<32 x s16>) into %ir.p_out.0, align 32, !tbaa !4, addrspace 7)
    %225:modregbank(s20) = G_CONSTANT i20 64
    %204:ptrregbank(p0) = G_AIE_POSTINC_STORE %201(<32 x s16>), %202, %225(s20) :: (store (<32 x s16>) into %ir.arrayidx.i.i.i.i.i.i.i.i.i.i.i12, align 32, !tbaa !4, addrspace 7)
    %206:gprregbank(s32) = nsw G_ADD %35, %205
    %211:gprregbank(s32) = G_ICMP intpred(eq), %206(s32), %56
    G_BRCOND %211(s32), %bb.5
    G_BR %bb.6

I think the best here is to have a transparent way to handle those concat/regseq/bitcast among all operations. What do you think?

[abhinay-anubola]

This was solved by: #195