Version bump to v0.2.1

Xilinx · Jun 2, 2021 · 0972aed · 0972aed
1 parent 52d7e7c
commit 0972aed
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Showing 3 changed files with 14 additions and 2 deletions.
diff --git a/python/pyxir/__init__.py b/python/pyxir/__init__.py
@@ -26,7 +26,7 @@
 from .graph.xop_registry import XOpRegistry, xop_register_op_layout_transform,\
     xop_register_op_transpose_transform
 
-__version__ = "0.2.0"
+__version__ = "0.2.1"
 
 
 device_r = TargetRegistry()

diff --git a/setup.py b/setup.py
@@ -35,7 +35,7 @@
 
 from pathlib import Path
 
-__version__ = '0.2.0'
+__version__ = '0.2.1'
 
 FILE_DIR = os.path.dirname(os.path.abspath(__file__))
 

diff --git a/version.txt b/version.txt
@@ -12,6 +12,18 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+//////////////// VERSION 0.2.1 ////////////////
+NEW FEATURES:
+    - /
+UPDATES:
+    - Add support for padding value argument instead of attribute in latest TVM Relay padding op
+BUG FIXES:
+    - Fix DNNC output parsing issue if non-alphabetic and/or non-numeric characters exist in
+      the output names 
+UNFIXED ISSUES:
+    - Importing tvm before pyxir results in segfault for DPUCADX8G env due to 
+      protobuf mismatch between DPUCADX8G tools and tensorflow
+
 //////////////// VERSION 0.2.0 ////////////////
 NEW FEATURES:
     - Create DPUCZDX8G (zcu104, zcu102, SOM and Ultra96) VART flow