DV Eng. @ PlanV · TUM M.Sc. · AI & Open-Source Verification Enthusiast
module Yilou_Wang_Career (
input logic clk,
input logic rst_n,
output logic [31:0] career_impact
);
// IF: Harbin Institute of Technology
localparam string IF_STAGE = "HIT · B.Sc. EE / Comm. Eng.";
// ID: Technical University of Munich
localparam string ID_STAGE = "TUM · M.Sc. EE / Comm. Eng.";
// EX: Infineon Technologies — Internship
localparam string EX_STAGE = "Infineon · SV / UVM / cocotb / pyuvm";
// MEM: PlanV — current role (active stage)
localparam string MEM_STAGE = "PlanV · Verification Engineer · Verilator / RISC-V / Open-Source Verification";
// WB: Life — AI & OSS enthusiast
localparam string WB_STAGE = "AI for Verification · Open Source EDA";
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) career_impact <= 32'h0;
else career_impact <= career_impact + 32'd1; // keep shipping
end
endmodule- 🎓 2017–2021: 🇨🇳 B.Eng. EE (Fuxin 🚄 Harbin)
- 🎓 2021–2024: 🇩🇪 M.Sc. EE @ TUM (China
✈️ Munich) - 🧪 Internship: NeuSoft & Infineon
- 💼 2024–now: DV Engineer @ PlanV
中文创作者轮播图引擎。把选题文案变成可渲染配置，并跑质量评分闭环。
DV playground for SV / UVM / Verilator / cocotb. Practical examples for onboarding and quick experiments.
- 🚀 verilator — contribution-aligned work fork.
- 🧪 PlanV_Verilator_Feature_Tests — feature validation flow at work.
- 📘 MS_Thesis_cocotb-BSHL — thesis implementation repo.
- 📄 Advancing Open-Source Verification: Enabling Full Randomization in Verilator — DVcon Europe 2025 · Oct 15, 2025
- 📄 Enable Reuse of SystemVerilog Verification IPs in cocotb/pyuvm — DVcon Europe 2024 · Oct 16, 2024
- #1 · 2024.08 · UVM in Verilator: Constraint random if/else
- #2 · 2024.10 · UVM in Verilator: CI system and test models
- #3 · 2024.11 · UVM in Verilator: Aggregate data type randomization
- #4 · 2025.02 · UVM in Verilator: Array constrained randomization
- #5 · 2025.07 · UVM in Verilator: Struct constrained randomization
- #6 · 2026.02 · 🤖 Verilator Gap Checker with AI
- Email: wangyilou123@gmail.com