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@YosysHQ

Yosys Headquarters

Yosys Open SYnthesis Suite
README.md

YosysHQ - Open Source EDA

OSS CAD Suite: the one-stop shop for our tools

If you want to use our EDA tools, the easiest way is to install the binary release OSS CAD suite, which contains all required dependencies and related tools. Find the documentation here. We also have an OSS CAD Suite github action for using the tools in a github CI workflow.

Tabby CAD Suite is a commercial extension of OSS CAD Suite available from YosysHQ GmbH that additionally includes the Verific frontend for industry-grade SystemVerilog and VHDL support, formal verification with SVA, and formal apps.

Our Projects

Front-ends for applications built on top of Yosys:

  • sby: formal property checking
  • mcy: mutation coverage
  • eqy: equivalence checking

Other notable projects:

  • riscv-formal: formally check compliance with the RISC-V specification
  • picorv32: A Size-Optimized RISC-V CPU
  • nerv: A very simple educational RISC-V CPU for demonstrating riscv-formal

Community

Support us

Like what we do? Please consider either buying a license for the Tabby CAD Suite or becoming a sponsor.

Pinned Loading

  1. yosys yosys Public

    Yosys Open SYnthesis Suite

    C++ 4.1k 1k

  2. nextpnr nextpnr Public

    nextpnr portable FPGA place and route tool

    C++ 1.5k 277

  3. sby sby Public

    SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

    Python 479 83

  4. oss-cad-suite-build oss-cad-suite-build Public

    Multi-platform nightly builds of open source digital design and verification tools

    Shell 1.2k 108

Repositories

Showing 10 of 41 repositories
  • yosys Public

    Yosys Open SYnthesis Suite

    YosysHQ/yosys’s past year of commit activity
    C++ 4,128 ISC 1,003 478 88 Updated Nov 15, 2025
  • oss-cad-suite-build Public

    Multi-platform nightly builds of open source digital design and verification tools

    YosysHQ/oss-cad-suite-build’s past year of commit activity
    Shell 1,231 ISC 108 72 7 Updated Nov 14, 2025
  • apicula Public

    Project Apicula 🐝: bitstream documentation for Gowin FPGAs

    YosysHQ/apicula’s past year of commit activity
    Verilog 595 MIT 79 18 3 Updated Nov 11, 2025
  • mcy Public

    Mutation Cover with Yosys (MCY)

    YosysHQ/mcy’s past year of commit activity
    C++ 88 ISC 14 1 1 Updated Nov 11, 2025
  • eqy Public

    Equivalence checking with Yosys

    YosysHQ/eqy’s past year of commit activity
    C++ 51 8 18 0 Updated Nov 11, 2025
  • sby Public

    SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

    YosysHQ/sby’s past year of commit activity
    Python 479 83 41 9 Updated Nov 11, 2025
  • abc Public Forked from berkeley-abc/abc

    ABC: System for Sequential Logic Synthesis and Formal Verification

    YosysHQ/abc’s past year of commit activity
    C 29 722 0 3 Updated Nov 11, 2025
  • prjpeppercorn Public

    Project Peppercorn - GateMate FPGA Bitstream Documentation

    YosysHQ/prjpeppercorn’s past year of commit activity
    Python 28 ISC 3 0 0 Updated Nov 10, 2025
  • nextpnr Public

    nextpnr portable FPGA place and route tool

    YosysHQ/nextpnr’s past year of commit activity
    C++ 1,548 ISC 277 107 (1 issue needs help) 10 Updated Nov 10, 2025
  • riscv-formal Public

    RISC-V Formal Verification Framework

    YosysHQ/riscv-formal’s past year of commit activity
    Verilog 166 ISC 36 6 3 Updated Nov 4, 2025
View all repositories

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