0.0.3

First usable alpha version. What should work is:

• the basic command line for vhdMMIO;
• markdown/mdbook documentation output for vhdMMIO itself;
• HTML documentation output for the generated register files;
• VHDL generation for primitive, interrupt, axi, and custom fields (and their derivatives).

What certainly does not work yet:

• memory fields;
• any kind of logic that is aware of more than one register file at a time (the idea is that register files can be connected hierarchically through AXI fields, and that the documentation and C/Python code for accessing the register files is automatically aware of this);
• C/Python code for accessing the register files (zero effort has been put into this so far).

Changes:

• 0ef939d Fix missing template files, autogen MANIFEST.in

This list of changes was auto generated.

0.0.2

NOTE: this release is broken; a couple template files were not included in the distribution. Use 0.0.3 instead.

Changes:

• 33baa91 Commented out memory field config
• e045cc4 Add alternative stream monitor example
• 6dcab25 Fix typo in field suffix generation
• 1bbe287 Fix typo in entity template
• fd6e1a0 Fix bug in custom field with internals
• ceb290c Fix missing end of sentence in documentation
• efd91b3 Fix lint errors, implement memory field config
• 389dd1b Add flattened bus mode for AXI fields
• 29151b9 Implement AXI fields
• ce81878 Add more tests for deferring fields + bugfixes

See more

• 2b228d5 Add tests for blocking & deferring fields + fixes
• b8cf2f9 Add tests for prot-based security + bugfixes
• 7d51cf8 Add additional tests for field repetition
• 7f3dbe7 Add tests for field repetition + bugfixes
• 5a37596 Add interface check to all integration tests
• d5cca05 Remove unused Parsed config loader
• 23b80bf Add tests for subaddresses + bugfixes
• 8705793 Remove dead VHDL code/TODO
• 89f1e07 Add test for custom regs with internals + bugfixes
• 12b0acc Minor bugfixes
• 70086a9 Add test for custom field state
• ace2b9e Save test case VHDL code when vhdeps launch fails
• 0a10c8a Add tests for custom field ports + bugfixes
• e4e67fe Add CLI tests for HTML and package generators
• 1657467 Add tests for entity output using CLI + bugfixes
• 475b333 Refactor examples
• 0a33457 Fix bdist_wheel not including all files
• 4278243 Clean up
• 1dd7909 Fix generated component declaration
• 7231690 Improve config test
• 5b3ecac Fix cyclic import for version string
• 0720f40 Print version info in all generated files
• f9fdffa Add entity configuration options
• 7c2f591 Add stream monitor example
• 8db1c34 Add code generation for subaddresses
• 7e2a150 Refactor field boilerplate template
• 5714d87 Add initial tests for custom registers + bugfixes
• 9319ce9 Implement custom behavior + unrelated bugfixes
• 5900e0e Define configuration structure for custom behavior
• ba6ea29 Refactor primitive behavior template
• 20321ff Add tests for stream registers + bugfixes
• f7cc798 Add tests for counter registers + bugfixes
• 3a08081 Add tests for request registers + bugfixes
• 2728a58 Add tests for flag registers + bugfixes
• 30f6e74 Add tests for control registers
• e7607e5 Add tests for status registers + bugfixes
• 3478504 Add tests for constant registers + bugfixes
• ce37ef2 Add tests for multi-word registers + bugfixes
• 8a6e95b Add tests for addressing and conditions + bugfixes
• 1313bf4 Add tests for interrupt fields + bugfixes
• 41166c4 Add tests for interrupt sensitivity + bugfixes
• 3809533 Fix version detection in setup.py
• 78b4ffa Merge branch 'configuration-cleanup'
• 7dc9e02 Update readme slightly
• 89cd0c3 Merge pull request #1 from abs-tudelft/configuration-cleanup
• e823a05 Fix CI pipeline
• 327c482 Put stream interface signals in canonical order
• 4522c00 Add tests for internals
• 305236b Implement VHDL codegen for primitive and interrupt
• 3bde23d Add 'wheel' to setup.py requirements
• d3f5042 Minor changes to interrupt logic template
• 117a83c Laid foundation for generating field logic again
• 1f9e099 Complete VHDL generation excluding field logic
• 44c70d2 Implement VHDL gen for internals + their I/O
• a3be842 Improve HTML tooltip consistency
• ef6cf5f Store blocks in address manager, expose signal map
• 95f99c2 Add rudimentary way to indent templates
• 5d888c2 Add option to make internal signals external
• e835e32 Fix header levels in generated docs
• ae33aa8 Add examples, clean up docs
• 5e610f4 Refactor test directory
• e75b014 Reintroduce register file testbench
• 3f33473 Refactor VHDL generator so it doesn't crash
• fab19da Refactored address decoder code
• 2c1b153 Add support for overlapping addresses to decoder
• f6d4f6c Tweaked HTML output
• f13c6d1 Fix some unknown keys not detected
• 6db4558 Implemented the majority of the HTML generator
• cfe8763 Bugfixes, WIP on HTML target
• 3727c77 Improve contextual errors
• e90c0af Implement interrupts
• 9eba405 Implement registers and blocks
• 0dbb0f5 Refactor for name consistency
• dde84dc Minor fixes/updates
• fee3d5c Modify addressing.py for register builders
• 1562f03 WIP on behavior code, add primitive
• 64cdf72 WIP on core
• f515b9e WIP on core
• e7077ce WIP on core
• 94705f6 Refactor mixins into own module, update AddressMgr
• b32a925 WIP on new core code
• bf11388 Update mdbook documentation
• f1103c9 Added configuration keys for advanced addressing
• d303a06 Refactored class names
• bcb024c WIP
• 9bb298a More refactoring
• f9447d0 Add basic integration test
• f497d87 Refactor + clean slate: delete all outdated
• 113a02f Re-add load/save API, perform basic tests manually
• 2e9c56e WIP on docs and config file structure
• 8452d18 WIP on docs and config file structure
• 6aa39de WIP on docs and config file structure
• 932b6d8 WIP on config file structure with new system
• cb300c1 Finish mutability/protection of configurables
• 680c988 Lots of refactoring in the config system
• 37c6d24 WIP
• 5dfe55d Added the last two configuration loaders
• 856900a Refactor @configurable code into its own module
• e0b9053 WIP cleaning up configuration code
• a1188c9 WIP cleaning up configuration code
• 553f26b Reorganize field logic submodules
• b3f9d97 Add .noseids to .gitignore
• 31a0518 Add tests for interrupt fields
• 104e2d9 Improved concepts document
• dbb723d Add internal signal support
• 4b7c11a Add tests for flag and counter fields
• c6393c4 Add more tests for primitive fields
• 464327d Add tests for control registers
• 99ec7b9 Add access method flags to ReadWriteCapabilities
• b849608 Improve coverage of vhdmmio.vhdl.interface
• 4f90f46 Add tests for metadata objects
• ae8240b Improve command line help
• 11903d2...

0.0.1

Initial version for testing purposes. Very little integration testing has been done so far, but what may work is:

• the basic command line for vhdMMIO;
• markdown/mdbook documentation output for vhdMMIO itself;
• HTML documentation output for the generated register files;
• VHDL generation for primitive and interrupt fields, plus all the support logic around it. This is the least tested part.

What certainly does not work yet:

• AXI, memory, and custom fields (the necessary subaddress code is also not entirely implemented yet);
• any kind of logic that is aware of more than one register file at a time (the idea is that register files can be connected hierarchically through AXI fields, and that the documentation and C/Python code for accessing the register files is automatically aware of this);
• C/Python code for accessing the register files (zero effort has been put into this so far).