WIP: stm32f7: Add support to I2S as alternative to SAI

arch/arm/src/stm32f7/CMakeLists.txt

@@ -33,8 +33,7 @@ list(
   stm32_start.c
   stm32_capture.c
   stm32_uid.c
-  stm32_waste.c
-)
+  stm32_waste.c)
 
 if(CONFIG_STM32F7_TICKLESS_TIMER)
   list(APPEND SRCS stm32_tickless.c)
@@ -94,6 +93,10 @@ if(CONFIG_STM32F7_I2C)
   list(APPEND SRCS stm32_i2c.c)
 endif()
 
+if(CONFIG_STM32F7_I2S)
+  list(APPEND SRCS stm32_i2s.c)
+endif()
+
 if(CONFIG_STM32F7_SPI)
   list(APPEND SRCS stm32_spi.c)
 endif()
@@ -110,9 +113,9 @@ if(CONFIG_USBHOST)
   list(APPEND SRCS stm32_otghost.c)
   if(CONFIG_USBHOST_TRACE)
     list(APPEND SRCS stm32_usbhost.c)
-    elseif(CONFIG_DEBUG_USB)
-      list(APPEND SRCS stm32_usbhost.c)
-    endif()
+  elseif(CONFIG_DEBUG_USB)
+    list(APPEND SRCS stm32_usbhost.c)
+  endif()
 endif()
 
 if(CONFIG_STM32F7_TIM)

arch/arm/src/stm32f7/Kconfig

@@ -1214,6 +1214,11 @@ config STM32F7_HAVE_EXTERNAL_ULPI
 	bool
 	default n
 
+config STM32F7_I2S
+	bool
+	default n
+	select STM32F7_SPI_DMA
+
 config STM32F7_HAVE_SAI1
 	bool
 	default n
@@ -1499,6 +1504,24 @@ config STM32F7_RNG
 	depends on STM32F7_HAVE_RNG
 	select ARCH_HAVE_RNG
 
+config STM32F7_I2S1
+	bool "I2S1"
+	default n
+	depends on !STM32F7_SPI1
+	select STM32F7_I2S
+
+config STM32F7_I2S2
+	bool "I2S2"
+	default n
+	depends on !STM32F7_SPI2
+	select STM32F7_I2S
+
+config STM32F7_I2S3
+	bool "I2S3"
+	default n
+	depends on !STM32F7_SPI3
+	select STM32F7_I2S
+
 config STM32F7_SAI1
 	bool "SAI1"
 	default n
@@ -2429,6 +2452,131 @@ config STM32F7_SPI6_DMA_BUFFER
 
 endmenu # "SPI Configuration"
 
+menu "I2S Configuration"
+	depends on STM32F7_I2S
+
+config STM32F7_I2S_MAXINFLIGHT
+	int "I2S queue size"
+	default 16
+	---help---
+		This is the total number of transfers, both RX and TX, that can be
+		enqueue before the caller is required to wait.  This setting
+		determines the number certain queue data structures that will be
+		pre-allocated.
+
+if STM32F7_I2S1
+
+comment "I2S1 Configuration"
+
+config STM32F7_I2S1_MCK
+	bool "I2S1_MCK"
+	default n
+	---help---
+		TBD.
+
+config STM32F7_I2S1_RX
+	bool "Enable I2S1 receiver"
+	default n
+	---help---
+		Enable I2S receipt logic
+
+config STM32F7_I2S1_TX
+	bool "Enable I2S1 transmitter"
+	default n
+	---help---
+		Enable I2S transmission logic
+
+config STM32F7_I2S1_DATALEN
+	int "I2S1 Data width (bits)"
+	default 16
+	---help---
+		Data width in bits.  This is a default value and may be change
+		via the I2S interface
+
+endif #STM32F7_I2S1
+
+if STM32F7_I2S2
+
+comment "I2S2 Configuration"
+
+config STM32F7_I2S2_MCK
+	bool "I2S2_MCK"
+	default n
+	---help---
+		TBD.
+
+config STM32F7_I2S2_RX
+	bool "Enable I2S2 receiver"
+	default n
+	---help---
+		Enable I2S receipt logic
+
+config STM32F7_I2S2_TX
+	bool "Enable I2S2 transmitter"
+	default n
+	---help---
+		Enable I2S transmission logic
+
+config STM32F7_I2S2_DATALEN
+	int "I2S2 Data width (bits)"
+	default 16
+	---help---
+		Data width in bits.  This is a default value and may be change
+		via the I2S interface
+
+endif #STM32F7_I2S2
+
+if STM32F7_I2S3
+
+comment "I2S3 Configuration"
+
+config STM32F7_I2S3_MCK
+	bool "I2S3_MCK"
+	default n
+	---help---
+		TBD.
+
+config STM32F7_I2S3_RX
+	bool "Enable I2S3 receiver"
+	default n
+	---help---
+		Enable I2S receipt logic
+
+config STM32F7_I2S3_TX
+	bool "Enable I2S3 transmitter"
+	default n
+	---help---
+		Enable I2S transmission logic
+
+config STM32_I2S3_DATALEN
+	int "I2S3 Data width (bits)"
+	default 16
+	---help---
+		Data width in bits.  This is a default value and may be change
+		via the I2S interface
+
+endif #STM32F7_I2S3
+
+config STM32_I2S_DMADEBUG
+	bool "I2S DMA transfer debug"
+	depends on DEBUG_DMA
+	default n
+	---help---
+		Enable special debug instrumentation analyze I2S DMA data transfers.
+		This logic is as non-invasive as possible:  It samples DMA
+		registers at key points in the data transfer and then dumps all of
+		the registers at the end of the transfer.
+
+config STM32_I2S_REGDEBUG
+	bool "SSC Register level debug"
+	depends on DEBUG
+	default n
+	---help---
+		Output detailed register-level SSC device debug information.
+		Very invasive! Requires also DEBUG.
+
+endmenu # I2S Configuration
+
 menu "I2C Configuration"
 	depends on STM32F7_I2C
 

arch/arm/src/stm32f7/Make.defs

@@ -93,6 +93,10 @@ ifeq ($(CONFIG_STM32F7_I2C),y)
 CHIP_CSRCS += stm32_i2c.c
 endif
 
+ifeq ($(CONFIG_STM32F7_I2S),y)
+CHIP_CSRCS += stm32_i2s.c
+endif
+
 ifeq ($(CONFIG_STM32F7_SPI),y)
 CHIP_CSRCS += stm32_spi.c
 endif