GitHub - alexandre-ss/Riscv-ucycle

Projeto e simulação do processador RISC-V uniciclo de 32 bits em VHDL

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
work		work
README.md		README.md
RISCV.cr.mti		RISCV.cr.mti
Riscv_uni.cr.mti		Riscv_uni.cr.mti
Riscv_uni.mpf		Riscv_uni.mpf
adder.vhd		adder.vhd
and.vhd		and.vhd
control.vhd		control.vhd
data.txt		data.txt
data_rv.vhd		data_rv.vhd
genImm32.vhd		genImm32.vhd
instruction.txt		instruction.txt
mux.vhd		mux.vhd
mux4.vhd		mux4.vhd
or.vhd		or.vhd
pc.vhd		pc.vhd
registers.vhd		registers.vhd
rom_rv.vhd		rom_rv.vhd
shift_left_func.vhd		shift_left_func.vhd
ulaRV.vhd		ulaRV.vhd
ula_control.vhd		ula_control.vhd
unicycle.vhd		unicycle.vhd
unicycle_tb.vhd		unicycle_tb.vhd
vsim.wlf		vsim.wlf

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