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Glayout PrePEX SPICE Generation #9

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wants to merge 55 commits into from
Closed

Glayout PrePEX SPICE Generation #9

wants to merge 55 commits into from

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harshkhandeparkar
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@harshkhandeparkar harshkhandeparkar commented Nov 17, 2023 •
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Changes

  • Added Netlist class for SPICE generation in glayout/spice/
  • Added prePEX SPICE netlists for primitive cells, diff pair, differential_to_single_ended_converter.
  • Added complete prePEX SPICE generation for the glayout op-amp.

@harshkhandeparkar
feat: added prepex spice generation code
97244cc
@harshkhandeparkar
feat: added prepex spice generation in mimcap
b7a8dcf
@harshkhandeparkar
feat: directly instantiated Netlist for mimcap
6723c97
@harshkhandeparkar
refactor: added default argument for circuit_name
af485da
@harshkhandeparkar
feat: added fet netlist
397d0e1
@harshkhandeparkar
fix: fixed typo
04b2920
@harshkhandeparkar
fix: used the correct keys in validation
f6923ab
@harshkhandeparkar
fix: fixed dummy tuple
5d5413c
@harshkhandeparkar
fix: fixed multiplier typo
29b7d78
@harshkhandeparkar
refactor: made generate_instance parameters optional
bcee192
@harshkhandeparkar
fix: fixed netlist generation
0a27836
@harshkhandeparkar
fix: renamed pmos subcircuit to PMOS
30e724c
@harshkhandeparkar
fix: fixed dummy fet multipliers
4882375
@harshkhandeparkar
feat: updated Netlist to support multiple subcircuits with same name
73ed4ee
@harshkhandeparkar
feat: added diff pair netlist
3f72a08
@harshkhandeparkar
feat: added differential to single netlist
9c878dc
@harshkhandeparkar
feat: added diff_pair_cmirrorbias netlist
4fd153b
@harshkhandeparkar
feat: added netlist for mimcap array
b03685e
@harshkhandeparkar
feat: added more netlists
f790d35
@harshkhandeparkar
feat: added input and gain stages' netlists
a2ef9ff
@harshkhandeparkar
fix: fixed netlist node naming issues
1f2fafe
@harshkhandeparkar
feat: named mimcap array netlist
4e79c65
@harshkhandeparkar
feat: connected miller capacitor netlist
0f01074
@harshkhandeparkar
feat: flattened mimcap_arr netlist
88d0543
@harshkhandeparkar
feat: completed output stage and top level netlists
bc0be6e
@harshkhandeparkar
fix: removed $ typo
69a22d8
@harshkhandeparkar
fix: fixed sky130 fet model names
4721660
@harshkhandeparkar
feat: renamed vbias to ibias
25e06cb
@harshkhandeparkar
fix: fixed mimcap pin order
0b1b0c9
@harshkhandeparkar
feat: renamed biases, used subcircuit instead of M and C, fixes
f6a04d7
@harshkhandeparkar
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cc @msaligane

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2 participants
@harshkhandeparkar @alibillalhammoud