Implement RFC 70: unify naming of MemoryMap resources and windows.

Fixes #69.

amaranth_soc/csr/bus.py

@@ -636,18 +636,16 @@ class Decoder(wiring.Component):
         Data width. See :class:`Interface`.
     alignment : int, power-of-2 exponent
         Window alignment. See :class:`..memory.MemoryMap`.
-    name : :class:`str`
-        Window name. Optional. See :class:`..memory.MemoryMap`.
 
     Attributes
     ----------
     bus : :class:`Interface`
         CSR bus providing access to subordinate buses.
     """
-    def __init__(self, *, addr_width, data_width, alignment=0, name=None):
+    def __init__(self, *, addr_width, data_width, alignment=0):
         super().__init__({"bus": In(Signature(addr_width=addr_width, data_width=data_width))})
         self.bus.memory_map = MemoryMap(addr_width=addr_width, data_width=data_width,
-                                        alignment=alignment, name=name)
+                                        alignment=alignment)
         self._subs = dict()
 
     def align_to(self, alignment):
@@ -657,10 +655,10 @@ def align_to(self, alignment):
         """
         return self.bus.memory_map.align_to(alignment)
 
-    def add(self, sub_bus, *, addr=None):
+    def add(self, sub_bus, *, name=None, addr=None):
         """Add a window to a subordinate bus.
 
-        See :meth:`MemoryMap.add_resource` for details.
+        See :meth:`MemoryMap.add_window` for details.
         """
         if isinstance(sub_bus, wiring.FlippedInterface):
             sub_bus_unflipped = flipped(sub_bus)
@@ -673,7 +671,7 @@ def add(self, sub_bus, *, addr=None):
             raise ValueError(f"Subordinate bus has data width {sub_bus.data_width}, which is not "
                              f"the same as decoder data width {self.bus.data_width}")
         self._subs[sub_bus.memory_map] = sub_bus
-        return self.bus.memory_map.add_window(sub_bus.memory_map, addr=addr)
+        return self.bus.memory_map.add_window(sub_bus.memory_map, name=name, addr=addr)
 
     def elaborate(self, platform):
         m = Module()
@@ -682,7 +680,7 @@ def elaborate(self, platform):
         r_data_fanin = 0
 
         with m.Switch(self.bus.addr):
-            for sub_map, (sub_pat, sub_ratio) in self.bus.memory_map.window_patterns():
+            for sub_map, sub_name, (sub_pat, sub_ratio) in self.bus.memory_map.window_patterns():
                 assert sub_ratio == 1
 
                 sub_bus = self._subs[sub_map]

amaranth_soc/csr/event.py

@@ -42,8 +42,6 @@ class EventMonitor(wiring.Component):
         CSR bus data width. See :class:`..csr.Interface`.
     alignment : int, power-of-2 exponent
         CSR address alignment. See :class:`..memory.MemoryMap`.
-    name : str
-        Window name. Optional. See :class:`..memory.MemoryMap`.
 
     Attributes
     ----------
@@ -75,9 +73,7 @@ def __init__(self, event_map, *, trigger="level", data_width, alignment=0, name=
             "src": Out(self._monitor.src.signature),
             "bus": In(self._mux.bus.signature),
         })
-        self.bus.memory_map = MemoryMap(addr_width=addr_width, data_width=data_width,
-                                        alignment=alignment, name=name)
-        self.bus.memory_map.add_window(self._mux.bus.memory_map)
+        self.bus.memory_map = self._mux.bus.memory_map
 
     def elaborate(self, platform):
         m = Module()

amaranth_soc/csr/reg.py

@@ -596,8 +596,6 @@ class Builder:
         Data width.
     granularity : :class:`int`
         Granularity. Optional, defaults to 8 bits.
-    name : :class:`str`
-        Name of the address range. Optional.
 
     Raises
     ------
@@ -609,10 +607,8 @@ class Builder:
         If ``granularity`` is not a positive integer.
     :exc:`ValueError`
         If ``granularity`` is not a divisor of ``data_width``
-    :exc:`TypeError`
-        If ``name`` is not a string, or is empty.
     """
-    def __init__(self, *, addr_width, data_width, granularity=8, name=None):
+    def __init__(self, *, addr_width, data_width, granularity=8):
         if not isinstance(addr_width, int) or addr_width <= 0:
             raise TypeError(f"Address width must be a positive integer, not {addr_width!r}")
         if not isinstance(data_width, int) or data_width <= 0:
@@ -624,13 +620,9 @@ def __init__(self, *, addr_width, data_width, granularity=8, name=None):
             raise ValueError(f"Granularity {granularity} is not a divisor of data width "
                              f"{data_width}")
 
-        if name is not None and not (isinstance(name, str) and name):
-            raise TypeError(f"Name must be a non-empty string, not {name!r}")
-
         self._addr_width  = addr_width
         self._data_width  = data_width
         self._granularity = granularity
-        self._name        = name
 
         self._registers   = dict()
         self._scope_stack = []
@@ -648,10 +640,6 @@ def data_width(self):
     def granularity(self):
         return self._granularity
 
-    @property
-    def name(self):
-        return self._name
-
     def freeze(self):
         """Freeze the builder.
 
@@ -765,16 +753,13 @@ def Index(self, index):
 
     def as_memory_map(self):
         self.freeze()
-        memory_map = MemoryMap(addr_width=self.addr_width, data_width=self.data_width,
-                               name=self.name)
+        memory_map = MemoryMap(addr_width=self.addr_width, data_width=self.data_width)
         for reg, reg_name, reg_offset in self._registers.values():
             if reg_offset is not None:
                 reg_addr = (reg_offset * self.granularity) // self.data_width
             else:
                 reg_addr = None
             reg_size = (reg.element.width + self.data_width - 1) // self.data_width
-            # TBD: should integers be allowed inside resource names?
-            reg_name = tuple(str(part) for part in reg_name)
             memory_map.add_resource(reg, name=reg_name, addr=reg_addr, size=reg_size,
                                     alignment=ceil_log2(reg_size))
         memory_map.freeze()

amaranth_soc/csr/wishbone.py

@@ -29,8 +29,8 @@ class WishboneCSRBridge(wiring.Component):
         CSR bus driven by the bridge.
     data_width : int
         Wishbone bus data width. Optional. If ``None``, defaults to ``csr_bus.data_width``.
-    name : str
-        Window name. Optional. See :class:`..memory.MemoryMap`.
+    name : :class:`..memory.MemoryMap.Name`
+        Window name. Optional.
 
     Attributes
     ----------
@@ -59,10 +59,10 @@ def __init__(self, csr_bus, *, data_width=None, name=None):
         super().__init__({"wb_bus": In(wb_sig)})
 
         self.wb_bus.memory_map = MemoryMap(addr_width=csr_bus.addr_width,
-                                           data_width=csr_bus.data_width, name=name)
+                                           data_width=csr_bus.data_width)
         # Since granularity of the Wishbone interface matches the data width of the CSR bus,
         # no width conversion is performed, even if the Wishbone data width is greater.
-        self.wb_bus.memory_map.add_window(csr_bus.memory_map)
+        self.wb_bus.memory_map.add_window(csr_bus.memory_map, name=name)
 
         self._csr_bus = csr_bus
 

amaranth_soc/gpio.py

@@ -237,8 +237,6 @@ def __init__(self, pin_count):
         CSR bus address width.
     data_width : :class:`int`
         CSR bus data width.
-    name : :class:`str`
-        CSR bus window name. Optional.
     input_stages : :class:`int`
         Number of synchronization stages between pin inputs and the :class:`~Peripheral.Input`
         register. Optional. Defaults to ``2``.
@@ -259,13 +257,13 @@ def __init__(self, pin_count):
     :exc:`TypeError`
         If ``input_stages`` is not a non-negative integer.
     """
-    def __init__(self, *, pin_count, addr_width, data_width, name=None, input_stages=2):
+    def __init__(self, *, pin_count, addr_width, data_width, input_stages=2):
         if not isinstance(pin_count, int) or pin_count <= 0:
             raise TypeError(f"Pin count must be a positive integer, not {pin_count!r}")
         if not isinstance(input_stages, int) or input_stages < 0:
             raise TypeError(f"Input stages must be a non-negative integer, not {input_stages!r}")
 
-        regs = csr.Builder(addr_width=addr_width, data_width=data_width, name=name)
+        regs = csr.Builder(addr_width=addr_width, data_width=data_width)
 
         self._mode   = regs.add("Mode",   self.Mode(pin_count))
         self._input  = regs.add("Input",  self.Input(pin_count))