csr.reg: rename wiring.Interface to wiring.PureInterface.

amaranth-lang · Dec 7, 2023 · f006384 · f006384
1 parent 3204e89
commit f006384
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/amaranth_soc/csr/reg.py b/amaranth_soc/csr/reg.py
@@ -10,7 +10,7 @@
 __all__ = ["FieldPort", "Field", "FieldMap", "FieldArray", "Register", "RegisterMap", "Bridge"]
 
 
-class FieldPort(wiring.Interface):
+class FieldPort(wiring.PureInterface):
     class Access(enum.Enum):
         """Field access mode."""
         R  = "r"
@@ -127,7 +127,7 @@ def __repr__(self):
     signature : :class:`FieldPort.Signature`
         Field port signature.
     path : iter(:class:`str`)
-        Path to the field port. Optional. See :class:`wiring.Interface`.
+        Path to the field port. Optional. See :class:`wiring.PureInterface`.
 
     Raises
     ------