csr.bus: fix incorrect flow of element members of register signatures.

amaranth-lang · May 21, 2024 · f21b31e · f21b31e
1 parent 1925de0
commit f21b31e
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Showing 4 changed files with 14 additions and 14 deletions.
diff --git a/amaranth_soc/csr/bus.py b/amaranth_soc/csr/bus.py
@@ -592,12 +592,12 @@ def _check_memory_map(self, memory_map):
             raise ValueError("CSR multiplexer memory map cannot have windows")
         for reg, reg_name, (reg_start, reg_end) in memory_map.resources():
             if not ("element" in reg.signature.members and
-                    reg.signature.members["element"].flow == Out and
+                    reg.signature.members["element"].flow == In and
                     reg.signature.members["element"].is_signature and
                     isinstance(reg.signature.members["element"].signature, Element.Signature)):
                 raise AttributeError(f"Signature of CSR register {reg_name} must have a "
                                      f"csr.Element.Signature member named 'element' and oriented "
-                                     f"as wiring.Out")
+                                     f"as wiring.In")
 
     def elaborate(self, platform):
         m = Module()

diff --git a/amaranth_soc/csr/reg.py b/amaranth_soc/csr/reg.py
@@ -437,7 +437,7 @@ class Register(wiring.Component):
 
     Members
     -------
-    element : :py:`Out(csr.Element.Signature(shape, access))`
+    element : :py:`In(csr.Element.Signature(shape, access))`
         Interface between this :class:`Register` and a CSR bus primitive.
 
     Raises
@@ -522,7 +522,7 @@ def filter_fields(src):
                 raise ValueError(f"Field {'__'.join(field_path)} is writable, but element access "
                                  f"mode is {access}")
 
-        super().__init__({"element": Out(Element.Signature(width, access))})
+        super().__init__({"element": In(Element.Signature(width, access))})
 
     @property
     def field(self):

diff --git a/tests/test_csr_bus.py b/tests/test_csr_bus.py
@@ -12,7 +12,7 @@
 
 class _MockRegister(wiring.Component):
     def __init__(self, width, access):
-        super().__init__({"element": Out(csr.Element.Signature(width, access))})
+        super().__init__({"element": In(csr.Element.Signature(width, access))})
 
 
 class ElementSignatureTestCase(unittest.TestCase):
@@ -204,32 +204,32 @@ class _Reg(wiring.Component):
             pass
         # wrong name
         map_0 = MemoryMap(addr_width=1, data_width=8)
-        map_0.add_resource(_Reg({"foo": Out(csr.Element.Signature(8, "rw"))}), name=("a",), size=1)
+        map_0.add_resource(_Reg({"foo": In(csr.Element.Signature(8, "rw"))}), name=("a",), size=1)
         with self.assertRaisesRegex(AttributeError,
                 r"Signature of CSR register \('a',\) must have a csr\.Element\.Signature member "
-                r"named 'element' and oriented as wiring\.Out"):
+                r"named 'element' and oriented as wiring\.In"):
             csr.Multiplexer(map_0)
         # wrong direction
         map_1 = MemoryMap(addr_width=1, data_width=8)
-        map_1.add_resource(_Reg({"element": In(csr.Element.Signature(8, "rw"))}), name=("a",),
+        map_1.add_resource(_Reg({"element": Out(csr.Element.Signature(8, "rw"))}), name=("a",),
                            size=1)
         with self.assertRaisesRegex(AttributeError,
                 r"Signature of CSR register \('a',\) must have a csr\.Element\.Signature member "
-                r"named 'element' and oriented as wiring\.Out"):
+                r"named 'element' and oriented as wiring\.In"):
             csr.Multiplexer(map_1)
         # wrong member type
         map_2 = MemoryMap(addr_width=1, data_width=8)
-        map_2.add_resource(_Reg({"element": Out(unsigned(8))}), name=("a",), size=1)
+        map_2.add_resource(_Reg({"element": In(unsigned(8))}), name=("a",), size=1)
         with self.assertRaisesRegex(AttributeError,
                 r"Signature of CSR register \('a',\) must have a csr\.Element\.Signature member "
-                r"named 'element' and oriented as wiring\.Out"):
+                r"named 'element' and oriented as wiring\.In"):
             csr.Multiplexer(map_2)
         # wrong member signature
         map_3 = MemoryMap(addr_width=1, data_width=8)
-        map_3.add_resource(_Reg({"element": Out(wiring.Signature({}))}), name=("a",), size=1)
+        map_3.add_resource(_Reg({"element": In(wiring.Signature({}))}), name=("a",), size=1)
         with self.assertRaisesRegex(AttributeError,
                 r"Signature of CSR register \('a',\) must have a csr\.Element\.Signature member "
-                r"named 'element' and oriented as wiring\.Out"):
+                r"named 'element' and oriented as wiring\.In"):
             csr.Multiplexer(map_3)
 
     def test_wrong_memory_map_windows(self):

diff --git a/tests/test_csr_wishbone.py b/tests/test_csr_wishbone.py
@@ -14,7 +14,7 @@
 class _MockRegister(wiring.Component):
     def __init__(self, width, name):
         super().__init__({
-            "element": Out(csr.Element.Signature(width, "rw")),
+            "element": In(csr.Element.Signature(width, "rw")),
             "r_count": Out(unsigned(8)),
             "w_count": Out(unsigned(8)),
             "data":    Out(width)