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wishbone.bus.Decoder: Only assert stb when slave is selected #31

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wishbone.bus.Decoder: Only assert stb when slave is selected #31

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6 changes: 4 additions & 2 deletions nmigen_soc/test/test_wishbone_bus.py
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Original file line number Diff line number Diff line change
Expand Up @@ -208,8 +208,9 @@ def sim_test():
yield Delay(1e-6)
self.assertEqual((yield sub_1.adr), 0x400 >> 2)
self.assertEqual((yield sub_1.cyc), 1)
self.assertEqual((yield sub_2.cyc), 0)
self.assertEqual((yield sub_1.stb), 1)
self.assertEqual((yield sub_2.cyc), 0)
self.assertEqual((yield sub_2.stb), 0)
self.assertEqual((yield sub_1.sel), 0b11)
self.assertEqual((yield sub_1.dat_w), 0x12345678)
self.assertEqual((yield dut.bus.ack), 1)
Expand All @@ -225,8 +226,9 @@ def sim_test():
yield Delay(1e-6)
self.assertEqual((yield sub_2.adr), 0x400 >> 2)
self.assertEqual((yield sub_1.cyc), 0)
self.assertEqual((yield sub_1.stb), 0)
self.assertEqual((yield sub_2.cyc), 1)
self.assertEqual((yield sub_1.stb), 1)
self.assertEqual((yield sub_2.stb), 1)
self.assertEqual((yield sub_1.sel), 0b11)
self.assertEqual((yield sub_1.dat_w), 0x12345678)
self.assertEqual((yield sub_2.lock), 1)
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2 changes: 1 addition & 1 deletion nmigen_soc/wishbone/bus.py
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Original file line number Diff line number Diff line change
Expand Up @@ -283,7 +283,6 @@ def elaborate(self, platform):
sub_bus.dat_w.eq(self.bus.dat_w),
sub_bus.sel.eq(Cat(Repl(sel, sub_ratio) for sel in self.bus.sel)),
sub_bus.we.eq(self.bus.we),
sub_bus.stb.eq(self.bus.stb),
]
if hasattr(sub_bus, "lock"):
m.d.comb += sub_bus.lock.eq(getattr(self.bus, "lock", 0))
Expand All @@ -295,6 +294,7 @@ def elaborate(self, platform):
granularity_bits = log2_int(self.bus.data_width // self.bus.granularity)
with m.Case(sub_pat[:-granularity_bits if granularity_bits > 0 else None]):
m.d.comb += [
sub_bus.stb.eq(self.bus.stb),
sub_bus.cyc.eq(self.bus.cyc),
self.bus.dat_r.eq(sub_bus.dat_r),
]
Expand Down