csr.bus: redesign Multiplexer shadow registers.

[jfng]

Before this commit, csr.Multiplexer had separate shadows for every element in its memory map. The same shadow was shared for read and write accesses to an Element; a combined read/write transaction was impossible despite being allowed by the CSR interface.

After this commit, csr.Multiplexer has separate shadows for read and write accesses, but both shadows are shared by every Element using them. For multiplexers with many elements, this approach also results in significant resource savings.

Example

To measure the resource savings, let's consider this example:

from amaranth import *
from amaranth.back import rtlil
from amaranth_soc import csr

mux = csr.Multiplexer(addr_width=1, data_width=8, alignment=2)

for i in range(8):
    a = csr.Element(32, "rw", name=f"a{i}")
    mux.add(a, extend=True)
    b = csr.Element( 8, "r",  name=f"b{i}")
    mux.add(b, extend=True)
    c = csr.Element( 8, "r",  name=f"c{i}")
    mux.add(c, extend=True)
    d = csr.Element(16, "w",  name=f"d{i}")
    mux.add(d, extend=True)

ports = [
    mux.bus.addr,
    mux.bus.r_stb,
    mux.bus.r_data,
    mux.bus.w_stb,
    mux.bus.w_data,
]
for e, _, _ in mux.bus.memory_map.resources():
    if e.access.readable():
        ports += [e.r_stb, e.r_data]
    if e.access.writable():
        ports += [e.w_stb, e.w_data]

print(rtlil.convert(mux, ports=ports))

Statistics

• Before this commit, yosys -p "synth_ecp5 -nowidelut" would report this:

=== top ===

   Number of wires:                602
   Number of wire bits:           2203
   Number of public wires:         602
   Number of public wire bits:    2203
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               1276
     LUT4                          700
     TRELLIS_FF                    576

• After this commit, with the default shadow_overlaps=None, yosys -p "synth_ecp5 -nowidelut" reports this:

=== top ===

   Number of wires:                218
   Number of wire bits:           1254
   Number of public wires:         218
   Number of public wire bits:    1254
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                437
     LUT4                          353
     TRELLIS_FF                     84

The new design uses 2x less LUT4s and 7x less FFs !

• With shadow_overlaps=3, yosys -p "synth_ecp5 -nowidelut" reports this:

=== top ===

   Number of wires:                335
   Number of wire bits:           1773
   Number of public wires:         335
   Number of public wire bits:    1773
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                662
     LUT4                          442
     TRELLIS_FF                    220

The shadow_overlaps parameter is exposed to users in case it proves useful, although LUT packing benefits seem to be outweighed by the increased cost in address decoding logic. None seem to be a good default for FPGAs, at least.

In these three cases, running nextpnr-ecp5 --out-of-context (or --pack-only) afterwards reports the same amount of LUTs/FFs.

[whitequark]

The new design uses 2x less LUT4s and 7x less FFs !

That's amazing! I expected the savings to be good but I didn't expect them to be this good.

[whitequark]

This is very nicely and cleanly implemented. Great job!

[jfng]

Merged, at last! Thank you @whitequark for providing the idea behind this redesign, and for reviewing it.

[whitequark]

Happy to have brought this to completion! This will be extremely useful.