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tests: fix warnings about unclosed VCD files. #88

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May 17, 2024
Merged

tests: fix warnings about unclosed VCD files. #88

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10 changes: 5 additions & 5 deletions tests/test_csr_action.py
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ def process():

sim = Simulator(dut)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()


Expand All @@ -49,7 +49,7 @@ def process():

sim = Simulator(dut)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()


Expand Down Expand Up @@ -82,7 +82,7 @@ def process():
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()


Expand Down Expand Up @@ -123,7 +123,7 @@ def process():
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()


Expand Down Expand Up @@ -164,7 +164,7 @@ def process():
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()


Expand Down
6 changes: 3 additions & 3 deletions tests/test_csr_bus.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -324,7 +324,7 @@ def sim_test():
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(sim_test)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()


Expand Down Expand Up @@ -362,7 +362,7 @@ def sim_test():
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(sim_test)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()


Expand Down Expand Up @@ -463,5 +463,5 @@ def sim_test():
sim = Simulator(m)
sim.add_clock(1e-6)
sim.add_testbench(sim_test)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()
2 changes: 1 addition & 1 deletion tests/test_csr_event.py
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ def simulation_test(dut, process):
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()


Expand Down
6 changes: 3 additions & 3 deletions tests/test_csr_reg.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -642,7 +642,7 @@ def process():
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()

def test_sim_single(self):
Expand Down Expand Up @@ -681,7 +681,7 @@ def process():
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()

class _MockRegister(Register, access="rw"):
Expand Down Expand Up @@ -1050,5 +1050,5 @@ def process():
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()
4 changes: 2 additions & 2 deletions tests/test_csr_wishbone.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -151,7 +151,7 @@ def sim_test():
sim = Simulator(m)
sim.add_clock(1e-6)
sim.add_testbench(sim_test)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()

def test_wide(self):
Expand Down Expand Up @@ -230,5 +230,5 @@ def sim_test():
sim = Simulator(m)
sim.add_clock(1e-6)
sim.add_testbench(sim_test)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()
2 changes: 1 addition & 1 deletion tests/test_event.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ def simulation_test(dut, process):
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(process)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()


Expand Down
4 changes: 2 additions & 2 deletions tests/test_gpio.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -330,7 +330,7 @@ def testbench():
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(testbench)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()

def test_sim_without_input_sync(self):
Expand All @@ -349,5 +349,5 @@ def testbench():
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(testbench)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()
16 changes: 8 additions & 8 deletions tests/test_wishbone_bus.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -283,7 +283,7 @@ def sim_test():

sim = Simulator(dut)
sim.add_testbench(sim_test)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()

def test_addr_translate(self):
Expand Down Expand Up @@ -394,7 +394,7 @@ def sim_test():
m.submodules += dut, loop_1, loop_2, loop_3, loop_4
sim = Simulator(m)
sim.add_testbench(sim_test)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()

def test_coarse_granularity(self):
Expand All @@ -416,7 +416,7 @@ def sim_test():

sim = Simulator(dut)
sim.add_testbench(sim_test)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()


Expand Down Expand Up @@ -534,7 +534,7 @@ def sim_test():
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(sim_test)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()

def test_lock(self):
Expand Down Expand Up @@ -587,7 +587,7 @@ def sim_test():
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(sim_test)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()

def test_stall(self):
Expand All @@ -613,7 +613,7 @@ def sim_test():

sim = Simulator(dut)
sim.add_testbench(sim_test)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()

def test_stall_compat(self):
Expand All @@ -638,7 +638,7 @@ def sim_test():

sim = Simulator(dut)
sim.add_testbench(sim_test)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()

def test_roundrobin(self):
Expand Down Expand Up @@ -700,5 +700,5 @@ def sim_test():
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_testbench(sim_test)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
with sim.write_vcd(vcd_file="test.vcd"):
sim.run()
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