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ad7616_sdz/zc706: Update spi namings
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StancaPop committed Sep 20, 2022
1 parent d8c655c commit 6167f15
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Showing 4 changed files with 24 additions and 16 deletions.
10 changes: 5 additions & 5 deletions projects/ad7616_sdz/zc706/serial_if_constr.xdc
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Expand Up @@ -3,11 +3,11 @@

# data interface

set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports spi_sdi[0]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports spi_sdi[1]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports spi_cs_n] ; ## FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sclk] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdo] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[0]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[1]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_cs_n] ; ## FMC_LPC_LA04_N

# control lines

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8 changes: 8 additions & 0 deletions projects/ad7616_sdz/zc706/system_bd.tcl
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Expand Up @@ -9,5 +9,13 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9

sysid_gen_sys_init_file

# system level parameters
set SI_OR_PI $ad_project_params(SI_OR_PI)

adi_project_files ad7616_sdz_zc706 [list \
"../../../library/common/ad_edge_detect.v" \
"../../../library/util_cdc/sync_bits.v" \
]

source ../common/ad7616_bd.tcl

2 changes: 1 addition & 1 deletion projects/ad7616_sdz/zc706/system_top_pi.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
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20 changes: 10 additions & 10 deletions projects/ad7616_sdz/zc706/system_top_si.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -73,10 +73,10 @@ module system_top (
inout iic_scl,
inout iic_sda,

output spi_sclk,
output spi_sdo,
input [ 1:0] spi_sdi,
output spi_cs_n,
output ad7616_spi_sclk,
output ad7616_spi_sdo,
input [ 1:0] ad7616_spi_sdi,
output ad7616_spi_cs_n,

output adc_reset_n,
output adc_convst,
Expand Down Expand Up @@ -152,11 +152,11 @@ module system_top (
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.spdif (spdif),
.rx_sclk (spi_sclk),
.rx_sdo (spi_sdo),
.rx_sdi (spi_sdi),
.rx_cnvst (adc_convst),
.rx_cs_n (spi_cs_n),
.ad7616_spi_sdo (ad7616_spi_sdo),
.ad7616_spi_sdi (ad7616_spi_sdi),
.ad7616_spi_cs (ad7616_spi_cs),
.ad7616_spi_sclk (ad7616_spi_sclk),
.rx_cnvst (adc_cnvst),
.rx_busy (adc_busy));

endmodule

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