ad7616_sdz/zc706: Update spi namings

analogdevicesinc · Sep 22, 2022 · e8892a6 · e8892a6
1 parent d20ca94
commit e8892a6
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Showing 5 changed files with 37 additions and 32 deletions.
diff --git a/projects/ad7616_sdz/zc706/parallel_if_constr.xdc b/projects/ad7616_sdz/zc706/parallel_if_constr.xdc
@@ -23,7 +23,7 @@ set_property -dict {PACKAGE_PIN AH13     IOSTANDARD LVCMOS25} [get_ports adc_wr_
 
 # control lines
 
-set_property -dict {PACKAGE_PIN AF30     IOSTANDARD LVCMOS25} [get_ports adc_convst]         ; ## FMC_LPC_LA24_P
+set_property -dict {PACKAGE_PIN AF30     IOSTANDARD LVCMOS25} [get_ports adc_cnvst]          ; ## FMC_LPC_LA24_P
 set_property -dict {PACKAGE_PIN AH29     IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]]       ; ## FMC_LPC_LA21_N
 set_property -dict {PACKAGE_PIN AK30     IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]]       ; ## FMC_LPC_LA26_N
 set_property -dict {PACKAGE_PIN AF29     IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]]       ; ## FMC_LPC_LA25_P

diff --git a/projects/ad7616_sdz/zc706/serial_if_constr.xdc b/projects/ad7616_sdz/zc706/serial_if_constr.xdc
@@ -3,15 +3,15 @@
 
 # data interface
 
-set_property -dict {PACKAGE_PIN AH12      IOSTANDARD LVCMOS25} [get_ports spi_sclk]            ; ## FMC_LPC_LA03_N
-set_property -dict {PACKAGE_PIN AB12      IOSTANDARD LVCMOS25} [get_ports spi_sdo]             ; ## FMC_LPC_LA06_P
-set_property -dict {PACKAGE_PIN AE13      IOSTANDARD LVCMOS25} [get_ports spi_sdi[0]]          ; ## FMC_LPC_LA00_CC_P
-set_property -dict {PACKAGE_PIN AG15      IOSTANDARD LVCMOS25} [get_ports spi_sdi[1]]          ; ## FMC_LPC_LA01_CC_N
-set_property -dict {PACKAGE_PIN AK15      IOSTANDARD LVCMOS25} [get_ports spi_cs_n]            ; ## FMC_LPC_LA04_N
+set_property -dict {PACKAGE_PIN AH12      IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sclk]     ; ## FMC_LPC_LA03_N
+set_property -dict {PACKAGE_PIN AB12      IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdo]      ; ## FMC_LPC_LA06_P
+set_property -dict {PACKAGE_PIN AE13      IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[0]]   ; ## FMC_LPC_LA00_CC_P
+set_property -dict {PACKAGE_PIN AG15      IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[1]]   ; ## FMC_LPC_LA01_CC_N
+set_property -dict {PACKAGE_PIN AK15      IOSTANDARD LVCMOS25} [get_ports ad7616_spi_cs_n]     ; ## FMC_LPC_LA04_N
 
 # control lines
 
-set_property -dict {PACKAGE_PIN AF30      IOSTANDARD LVCMOS25} [get_ports adc_convst]          ; ## FMC_LPC_LA24_P
+set_property -dict {PACKAGE_PIN AF30      IOSTANDARD LVCMOS25} [get_ports adc_cnvst]           ; ## FMC_LPC_LA24_P
 set_property -dict {PACKAGE_PIN AH29      IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]]        ; ## FMC_LPC_LA21_N
 set_property -dict {PACKAGE_PIN AK30      IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]]        ; ## FMC_LPC_LA26_N
 set_property -dict {PACKAGE_PIN AF29      IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]]        ; ## FMC_LPC_LA25_P

diff --git a/projects/ad7616_sdz/zc706/system_bd.tcl b/projects/ad7616_sdz/zc706/system_bd.tcl
@@ -9,5 +9,12 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
 
 sysid_gen_sys_init_file
 
+# system level parameters
+set SI_OR_PI $ad_project_params(SI_OR_PI)
+
+adi_project_files ad7616_sdz_zc706 [list \
+	"../../../library/common/ad_edge_detect.v" \
+	"../../../library/util_cdc/sync_bits.v"]
+
 source ../common/ad7616_bd.tcl
 
diff --git a/projects/ad7616_sdz/zc706/system_top_pi.v b/projects/ad7616_sdz/zc706/system_top_pi.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
+// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -79,7 +79,7 @@ module system_top (
 
   output                  adc_cs_n,
   output                  adc_reset_n,
-  output                  adc_convst,
+  output                  adc_cnvst,
   input                   adc_busy,
   output                  adc_seq_en,
   output      [ 1:0]      adc_hw_rngsel,
@@ -96,8 +96,6 @@ module system_top (
   wire    [15:0]  adc_db_o;
   wire    [15:0]  adc_db_i;
 
-  genvar i;
-
   // instantiations
 
   ad_iobuf #(
@@ -111,15 +109,15 @@ module system_top (
              adc_seq_en,         // 37
              adc_chsel}));       // 35:33
 
-  generate
-    for (i = 0; i < 16; i = i + 1) begin: adc_db_io
-      ad_iobuf i_iobuf_adc_db (
-        .dio_t(adc_db_t),
-        .dio_i(adc_db_o[i]),
-        .dio_o(adc_db_i[i]),
-        .dio_p(adc_db[i]));
-    end
-  endgenerate
+  assign gpio_i[63:44] = ghpio_o[63:44];
+
+  ad_iobuf #(
+    .DATA_WIDTH(16)
+  ) i_iobuf_adc_db (
+    .dio_t(adc_db_t),
+    .dio_i(adc_db_o[15:0]),
+    .dio_o(adc_db_i[15:0]),
+    .dio_p(adc_db[15:0]));
 
   ad_iobuf #(
     .DATA_WIDTH(15)
@@ -162,7 +160,7 @@ module system_top (
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .spdif (spdif),
-    .rx_cnvst (adc_convst),
+    .rx_cnvst (adc_cnvst),
     .rx_cs_n (adc_cs_n),
     .rx_busy (adc_busy),
     .rx_db_o (adc_db_o),

diff --git a/projects/ad7616_sdz/zc706/system_top_si.v b/projects/ad7616_sdz/zc706/system_top_si.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
+// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -73,13 +73,13 @@ module system_top (
   inout                   iic_scl,
   inout                   iic_sda,
 
-  output                  spi_sclk,
-  output                  spi_sdo,
-  input       [ 1:0]      spi_sdi,
-  output                  spi_cs_n,
+  output                  ad7616_spi_sclk,
+  output                  ad7616_spi_sdo,
+  input       [ 1:0]      ad7616_spi_sdi,
+  output                  ad7616_spi_cs_n,
 
   output                  adc_reset_n,
-  output                  adc_convst,
+  output                  adc_cnvst,
   input                   adc_busy,
   output                  adc_seq_en,
   output      [ 1:0]      adc_hw_rngsel,
@@ -152,11 +152,11 @@ module system_top (
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .spdif (spdif),
-    .rx_sclk (spi_sclk),
-    .rx_sdo (spi_sdo),
-    .rx_sdi (spi_sdi),
-    .rx_cnvst (adc_convst),
-    .rx_cs_n (spi_cs_n),
+    .ad7616_spi_sdo (ad7616_spi_sdo),
+    .ad7616_spi_sdi (ad7616_spi_sdi),
+    .ad7616_spi_cs (ad7616_spi_cs),
+    .ad7616_spi_sclk (ad7616_spi_sclk),
+    .rx_cnvst (adc_cnvst),
     .rx_busy (adc_busy));
 
 endmodule