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axi_dac_interpolate: Add raw value support
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Through this changes a user can set the dac output to a fixed predefined
value in the following two cases:
1. direct, without using the dma.
2. with dma, as a hold value. The fixed value will be kipped after a cyclic
buffer is stopped by axi_dac_interpolate, through dma_transfer_suspend
register/signal.
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@AndreiGrozav
AndreiGrozav committed Sep 26, 2023
1 parent 2d62ac3 commit fd675b7
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Showing 3 changed files with 67 additions and 25 deletions.
22 changes: 16 additions & 6 deletions library/axi_dac_interpolate/axi_dac_interpolate.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -124,7 +124,7 @@ module axi_dac_interpolate #(
wire [ 2:0] filter_mask_b;

wire dma_transfer_suspend;
wire flush_dma_in;
wire flush_dma_s;
wire start_sync_channels;

wire dac_correction_enable_a;
Expand Down Expand Up @@ -153,6 +153,9 @@ module axi_dac_interpolate #(
wire underflow_b;

wire stop_sync_channels;
wire raw_transfer_en;
wire [15:0] dac_raw_ch_a_data;
wire [15:0] dac_raw_ch_b_data;

// signal name changes

Expand Down Expand Up @@ -216,7 +219,6 @@ module axi_dac_interpolate #(
.dac_data (dac_data_a),
.dac_valid (dac_valid_a),
.dac_valid_out (dac_valid_out_a),
.sync_stop_channels (stop_sync_channels),

.dac_enable (dac_enable_a),
.dac_int_data (dac_int_data_a),
Expand All @@ -226,8 +228,11 @@ module axi_dac_interpolate #(
.filter_mask (filter_mask_a),
.interpolation_ratio (interpolation_ratio_a),
.dma_transfer_suspend (dma_transfer_suspend),
.flush_dma_in (flush_dma_in),
.start_sync_channels (start_sync_channels),
.sync_stop_channels (stop_sync_channels),
.flush_dma_in (flush_dma_s),
.raw_transfer_en (raw_transfer_en),
.dac_raw_ch_data (dac_raw_ch_a_data),
.trigger (trigger),
.trigger_active (trigger_active),
.en_start_trigger (en_start_trigger),
Expand All @@ -246,7 +251,6 @@ module axi_dac_interpolate #(
.dac_data (dac_data_b),
.dac_valid (dac_valid_b),
.dac_valid_out (dac_valid_out_b),
.sync_stop_channels (stop_sync_channels),
.underflow (underflow_b),

.dac_enable (dac_enable_b),
Expand All @@ -256,8 +260,11 @@ module axi_dac_interpolate #(
.filter_mask (filter_mask_b),
.interpolation_ratio (interpolation_ratio_b),
.dma_transfer_suspend (dma_transfer_suspend),
.flush_dma_in (flush_dma_in),
.start_sync_channels (start_sync_channels),
.sync_stop_channels (stop_sync_channels),
.flush_dma_in (flush_dma_s),
.raw_transfer_en (raw_transfer_en),
.dac_raw_ch_data (dac_raw_ch_b_data),
.trigger (trigger),
.trigger_active (trigger_active),
.en_start_trigger (en_start_trigger),
Expand All @@ -277,7 +284,10 @@ module axi_dac_interpolate #(
.dac_filter_mask_b (filter_mask_b),

.dma_transfer_suspend (dma_transfer_suspend),
.flush_dma_in (flush_dma_in),
.flush_dma_out (flush_dma_s),
.raw_transfer_en (raw_transfer_en),
.dac_raw_ch_a_data (dac_raw_ch_a_data),
.dac_raw_ch_b_data (dac_raw_ch_b_data),
.start_sync_channels (start_sync_channels),
.dac_correction_enable_a(dac_correction_enable_a),
.dac_correction_enable_b(dac_correction_enable_b),
Expand Down
33 changes: 24 additions & 9 deletions library/axi_dac_interpolate/axi_dac_interpolate_filter.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,16 +49,18 @@ module axi_dac_interpolate_filter #(
output reg [15:0] dac_int_data,
output dma_ready,
output dac_valid_out,
input sync_stop_channels,
output underflow,

input [ 2:0] filter_mask,
input [31:0] interpolation_ratio,
input [15:0] dac_correction_coefficient,
input dac_correction_enable,
input dma_transfer_suspend,
input flush_dma_in,
input start_sync_channels,
input sync_stop_channels,
input flush_dma_in,
input raw_transfer_en,
input [15:0] dac_raw_ch_data,
input trigger,
input trigger_active,
input en_start_trigger,
Expand All @@ -69,9 +71,9 @@ module axi_dac_interpolate_filter #(

// local parameters

localparam IDLE = 0;
localparam READY_TO_FLUSH = 1;
localparam FLUSHING = 1;
localparam [1:0] IDLE = 0;
localparam [1:0] READY_TO_FLUSH = 1;
localparam [1:0] FLUSHING = 2;

// internal signals

Expand All @@ -91,8 +93,9 @@ module axi_dac_interpolate_filter #(
reg [15:0] dma_valid_m = 16'd0;
reg stop_transfer = 1'd0;

reg flush_sm = 2'd0;
reg flush_sm_next = 2'd0;
reg [ 1:0] flush_sm = 2'd0;
reg [ 1:0] flush_sm_next = 2'd0;
reg raw_dma_n = 2'd0;

wire dac_valid_corrected;
wire [15:0] dac_data_corrected;
Expand All @@ -106,14 +109,26 @@ module axi_dac_interpolate_filter #(
wire dma_valid_ch;
wire flush_dma;

wire [15:0] iqcor_data_in;
wire iqcor_valid_in;

always @(posedge dac_clk) begin
raw_dma_n <= raw_transfer_en ?
1'b1 :
flush_dma | raw_dma_n & dma_transfer_suspend;
end

assign iqcor_data_in = raw_dma_n ? dac_raw_ch_data : dac_data;
assign iqcor_valid_in = raw_dma_n ? 1'b1 : dac_valid;

ad_iqcor #(
.Q_OR_I_N (0),
.DISABLE(CORRECTION_DISABLE),
.SCALE_ONLY(1)
) i_ad_iqcor (
.clk (dac_clk),
.valid (dac_valid),
.data_in (dac_data),
.valid (iqcor_valid_in),
.data_in (iqcor_data_in),
.data_iq (16'h0),
.valid_out (dac_valid_corrected),
.data_out (dac_data_corrected),
Expand Down
37 changes: 27 additions & 10 deletions library/axi_dac_interpolate/axi_dac_interpolate_reg.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,10 @@ module axi_dac_interpolate_reg(
output [31:0] dac_interpolation_ratio_b,
output [ 2:0] dac_filter_mask_b,
output dma_transfer_suspend,
output flush_dma_in,
output flush_dma_out,
output raw_transfer_en,
output [15:0] dac_raw_ch_a_data,
output [15:0] dac_raw_ch_b_data,
output start_sync_channels,
output stop_sync_channels,
output dac_correction_enable_a,
Expand Down Expand Up @@ -75,18 +78,21 @@ module axi_dac_interpolate_reg(
reg [ 2:0] up_filter_mask_a = 3'h0;
reg [31:0] up_interpolation_ratio_b = 32'h0;
reg [ 2:0] up_filter_mask_b = 3'h0;
reg [ 3:0] up_flags = 4'h2;
reg [ 4:0] up_flags = 5'ha;
reg [ 1:0] up_config = 2'h0;
reg [15:0] up_correction_coefficient_a = 16'h0;
reg [15:0] up_correction_coefficient_b = 16'h0;
reg [19:0] up_trigger_config = 20'h0;
reg [15:0] up_dac_raw_ch_a_data;
reg [15:0] up_dac_raw_ch_b_data;

wire [ 3:0] flags;
wire [ 4:0] flags;

assign dma_transfer_suspend = flags[0];
assign start_sync_channels = flags[1];
assign stop_sync_channels = flags[2];
assign flush_dma_in = flags[3];
assign flush_dma_out = flags[3];
assign raw_transfer_en = flags[4];

always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
Expand All @@ -96,11 +102,13 @@ module axi_dac_interpolate_reg(
up_filter_mask_a <= 'd0;
up_interpolation_ratio_b <= 'd0;
up_filter_mask_b <= 'd0;
up_flags <= 'd2;
up_flags <= 'ha;
up_config <= 'd0;
up_correction_coefficient_a <= 'd0;
up_correction_coefficient_b <= 'd0;
up_trigger_config <= 'd0;
up_dac_raw_ch_a_data <= 16'd0;
up_dac_raw_ch_b_data <= 16'd0;
end else begin
up_wack <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
Expand All @@ -119,7 +127,7 @@ module axi_dac_interpolate_reg(
up_filter_mask_b <= up_wdata[2:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
up_flags <= up_wdata[3:0];
up_flags <= up_wdata[4:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h15)) begin
up_config <= up_wdata[1:0];
Expand All @@ -133,6 +141,10 @@ module axi_dac_interpolate_reg(
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h18)) begin
up_trigger_config <= up_wdata[19:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h19)) begin
up_dac_raw_ch_a_data <= up_wdata[15:0];
up_dac_raw_ch_b_data <= up_wdata[31:16];
end
end
end

Expand All @@ -152,11 +164,12 @@ module axi_dac_interpolate_reg(
5'h11: up_rdata <= {29'h0,up_filter_mask_a};
5'h12: up_rdata <= up_interpolation_ratio_b;
5'h13: up_rdata <= {29'h0,up_filter_mask_b};
5'h14: up_rdata <= {28'h0,up_flags};
5'h14: up_rdata <= {27'h0,up_flags};
5'h15: up_rdata <= {30'h0,up_config};
5'h16: up_rdata <= {16'h0,up_correction_coefficient_a};
5'h17: up_rdata <= {16'h0,up_correction_coefficient_b};
5'h18: up_rdata <= {12'h0,up_trigger_config};
5'h19: up_rdata <= {up_dac_raw_ch_b_data, up_dac_raw_ch_a_data};
default: up_rdata <= 0;
endcase
end else begin
Expand All @@ -166,7 +179,7 @@ module axi_dac_interpolate_reg(
end

up_xfer_cntrl #(
.DATA_WIDTH(128)
.DATA_WIDTH(161)
) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
Expand All @@ -175,7 +188,9 @@ module axi_dac_interpolate_reg(
up_correction_coefficient_b,// 16
up_correction_coefficient_a,// 16
up_trigger_config, // 20
up_flags, // 4
up_flags, // 5
up_dac_raw_ch_a_data, // 16
up_dac_raw_ch_b_data, // 16
up_interpolation_ratio_b, // 32
up_interpolation_ratio_a, // 32
up_filter_mask_b, // 3
Expand All @@ -189,7 +204,9 @@ module axi_dac_interpolate_reg(
dac_correction_coefficient_b, // 16
dac_correction_coefficient_a, // 16
trigger_config, // 20
flags, // 4
flags, // 5
dac_raw_ch_a_data, // 16
dac_raw_ch_b_data, // 16
dac_interpolation_ratio_b, // 32
dac_interpolation_ratio_a, // 32
dac_filter_mask_b, // 3
Expand Down

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