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axi_jesd204_rx: Fixup write to up_cfg_buffer_delay #1186
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This change was introduced at #993 (direct link). looks like a mistake. |
Change up_cfg_buffer_delay assignment from up_wdata [7:0] to [9:2]. At register x90, up_cfg_buffer_delay occupies [9:2], but was being assigned up_wdata[7:0]. Due to this, tb/axi_jesd204_rx_regmap_tb was failing. Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Change up_cfg_buffer_delay bits to 9:2. Set 1:0 as RESERVED, since no driver implements it and is locked in 2'b00. Signed-off-by: Jorge Marques <jorge.marques@analog.com>
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Looking into https://github.com/analogdevicesinc/linux/blob/main/drivers/iio/jesd204/axi_jesd204_rx.c#L53 (DWORD 90, BYTE 240) Initially I expected to add more commits to this pr, but since it stayed untouched for so long, let's merge only this change. |
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Tested, working
Change up_cfg_buffer_delay assignment from up_wdata [7:0] to [9:2]. At register x90, up_cfg_buffer_delay occupies [9:2], but was being assigned up_wdata[7:0]. Due to this, tb/axi_jesd204_rx_regmap_tb was failing. Set 1:0 as RESERVED, since no driver implements it and is locked in 2'b00. Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Change up_cfg_buffer_delay assignment from up_wdata [7:0] to [9:2].
PR Description
Test axi_jesd204_rx_regmap_tb.v was failing at register x90 with output:
The issue is at fields Buffer release delay [9:2] and Data path width alignment [1:0], the latter is always 2'b00.
Investigating jesd204_up_rx.v, I noticed that up_cfg_buffer_delay is assigned up_wdata[7:0] instead of [9:2], incoherent with the read instruction.
I ran all tests at tb and now all succeeds (xsim, 2023.1).
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