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Fix copyrights and update AFE
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@sihyung-maxim
sihyung-maxim committed Jul 2, 2024
1 parent 20aa734 commit 5029005
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Showing 14 changed files with 74 additions and 310 deletions.
114 changes: 0 additions & 114 deletions Libraries/CMSIS/Device/Maxim/MAX32675/Include/aes_key_regs.h
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24 changes: 12 additions & 12 deletions Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_one_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -352,20 +352,20 @@ extern "C" {
*/
#define MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS 0 /**< CTRL_REF_SEL Position */
#define MXC_F_AFE_ADC_ONE_CTRL_REF_SEL ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS)) /**< CTRL_REF_SEL Mask */
#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */
#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */
#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Value */
#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Setting */
#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N ((uint8_t)0x1UL) /**< CTRL_REF_SEL_REF1P_AND_REF1N Value */
#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_REF1N Setting */
#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_REF2N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF2P_AND_REF2N Value */
#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_REF2N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_REF2N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_REF2N Setting */
#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND ((uint8_t)0x3UL) /**< CTRL_REF_SEL_AVDD_AND_AGND Value */
#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AVDD_AND_AGND Setting */
#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND ((uint8_t)0x4UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */
#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */
#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND ((uint8_t)0x5UL) /**< CTRL_REF_SEL_REF1P_AND_AGND Value */
#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_AGND Setting */
#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_AGND ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF2P_AND_AGND Value */
#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF2P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_AGND Setting */
#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */
#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */
#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_VDDA_AND_VSSA ((uint8_t)0x3UL) /**< CTRL_REF_SEL_VDDA_AND_VSSA Value */
#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_VDDA_AND_VSSA (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_VDDA_AND_VSSA << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_VDDA_AND_VSSA Setting */
#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_VSSA ((uint8_t)0x4UL) /**< CTRL_REF_SEL_AIN0P_AND_VSSA Value */
#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_VSSA (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_VSSA << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_VSSA Setting */
#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_VSSA ((uint8_t)0x5UL) /**< CTRL_REF_SEL_REF1P_AND_VSSA Value */
#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_VSSA (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_VSSA << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_VSSA Setting */
#define MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_VSSA ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF0P_AND_VSSA Value */
#define MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_VSSA (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_VSSA << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_VSSA Setting */

#define MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN_POS 3 /**< CTRL_REFBUFN_EN Position */
#define MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN_POS)) /**< CTRL_REFBUFN_EN Mask */
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24 changes: 12 additions & 12 deletions Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h
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Expand Up @@ -352,20 +352,20 @@ extern "C" {
*/
#define MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS 0 /**< CTRL_REF_SEL Position */
#define MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS)) /**< CTRL_REF_SEL Mask */
#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */
#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */
#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AIN1N ((uint8_t)0x0UL) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Value */
#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AIN1N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_AIN1N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_AIN1N Setting */
#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_REF1N ((uint8_t)0x1UL) /**< CTRL_REF_SEL_REF1P_AND_REF1N Value */
#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_REF1N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_REF1N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_REF1N Setting */
#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_REF2N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF2P_AND_REF2N Value */
#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_REF2N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_REF2N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_REF2N Setting */
#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AVDD_AND_AGND ((uint8_t)0x3UL) /**< CTRL_REF_SEL_AVDD_AND_AGND Value */
#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_AVDD_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AVDD_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AVDD_AND_AGND Setting */
#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND ((uint8_t)0x4UL) /**< CTRL_REF_SEL_REF0P_AND_AGND Value */
#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_AGND Setting */
#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_AGND ((uint8_t)0x5UL) /**< CTRL_REF_SEL_REF1P_AND_AGND Value */
#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_AGND Setting */
#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_AGND ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF2P_AND_AGND Value */
#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_AGND (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF2P_AND_AGND << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF2P_AND_AGND Setting */
#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x2UL) /**< CTRL_REF_SEL_REF0P_AND_REF0N Value */
#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_REF0N Setting */
#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_VDDA_AND_VSSA ((uint8_t)0x3UL) /**< CTRL_REF_SEL_VDDA_AND_VSSA Value */
#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_VDDA_AND_VSSA (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_VDDA_AND_VSSA << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_VDDA_AND_VSSA Setting */
#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_VSSA ((uint8_t)0x4UL) /**< CTRL_REF_SEL_AIN0P_AND_VSSA Value */
#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_VSSA (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_AIN0P_AND_VSSA << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_AIN0P_AND_VSSA Setting */
#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_VSSA ((uint8_t)0x5UL) /**< CTRL_REF_SEL_REF1P_AND_VSSA Value */
#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_VSSA (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF1P_AND_VSSA << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF1P_AND_VSSA Setting */
#define MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_VSSA ((uint8_t)0x6UL) /**< CTRL_REF_SEL_REF0P_AND_VSSA Value */
#define MXC_S_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_VSSA (MXC_V_AFE_ADC_ZERO_CTRL_REF_SEL_REF0P_AND_VSSA << MXC_F_AFE_ADC_ZERO_CTRL_REF_SEL_POS) /**< CTRL_REF_SEL_REF0P_AND_VSSA Setting */

#define MXC_F_AFE_ADC_ZERO_CTRL_REFBUFN_EN_POS 3 /**< CTRL_REFBUFN_EN Position */
#define MXC_F_AFE_ADC_ZERO_CTRL_REFBUFN_EN ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ZERO_CTRL_REFBUFN_EN_POS)) /**< CTRL_REFBUFN_EN Mask */
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4 changes: 2 additions & 2 deletions Libraries/CMSIS/Device/Maxim/MAX32675/Include/crc_regs.h
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Expand Up @@ -77,8 +77,8 @@ typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> CRC CTRL Register */
union {
__IO uint32_t datain32; /**< <tt>\b 0x0004:</tt> CRC DATAIN32 Register */
__IO uint16_t datain16[2]; /**< <tt>\b 0x0004:</tt> CRC DATAIN16 Register */
__IO uint8_t datain8[4]; /**< <tt>\b 0x0004:</tt> CRC DATAIN8 Register */
__IO uint16_t datain16; /**< <tt>\b 0x0004:</tt> CRC DATAIN16 Register */
__IO uint8_t datain8; /**< <tt>\b 0x0004:</tt> CRC DATAIN8 Register */
};
__IO uint32_t poly; /**< <tt>\b 0x0008:</tt> CRC POLY Register */
__IO uint32_t val; /**< <tt>\b 0x000C:</tt> CRC VAL Register */
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2 changes: 1 addition & 1 deletion Libraries/CMSIS/Device/Maxim/MAX32675/Include/dma_regs.h
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Expand Up @@ -88,7 +88,7 @@ typedef struct {
__IO uint32_t inten; /**< <tt>\b 0x000:</tt> DMA INTEN Register */
__I uint32_t intfl; /**< <tt>\b 0x004:</tt> DMA INTFL Register */
__R uint32_t rsv_0x8_0xff[62];
__IO mxc_dma_ch_regs_t ch[8]; /**< <tt>\b 0x100:</tt> DMA CH Register */
__IO mxc_dma_ch_regs_t ch[8]; /**< <tt>\b 0x100:</tt> DMA CH Register */
} mxc_dma_regs_t;

/* Register offsets for module DMA */
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8 changes: 2 additions & 6 deletions Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd
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Expand Up @@ -361,9 +361,7 @@
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>2</dimIncrement>
<name>DATAIN16[%s]</name>
<name>DATAIN16</name>
<description>CRC Data Input</description>
<addressOffset>0x0004</addressOffset>
<size>16</size>
Expand All @@ -379,9 +377,7 @@
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>1</dimIncrement>
<name>DATAIN8[%s]</name>
<name>DATAIN8</name>
<description>CRC Data Input</description>
<addressOffset>0x0004</addressOffset>
<size>8</size>
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114 changes: 0 additions & 114 deletions Libraries/CMSIS/Device/Maxim/MAX32680/Include/aes_key_regs.h
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