The modifications on the SDHC related driver codes for the remaining …

…micros (ME10, ME13 and AI87) is done.

Libraries/CMSIS/Device/Maxim/MAX32650/Include/system_max32650.h

@@ -46,8 +46,8 @@ extern "C" {
 #define NANORING_FREQ 8000
 #endif
 
-#ifndef HIRC96_FREQ
-#define HIRC96_FREQ 120000000
+#ifndef HIRC120_FREQ
+#define HIRC120_FREQ 120000000
 #endif
 
 #ifndef HIRC8_FREQ

Libraries/PeriphDrivers/Source/SDHC/sdhc_ai87.c

@@ -68,17 +68,17 @@ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg)
 unsigned int MXC_SDHC_Get_Input_Clock_Freq(void)
 {
     // Figure 4-1 of the preliminary AI85 UG (04/01/2022) shows the SDHC hardware block
-    // connected directly to the SYS_CLK node.  This is most likely inaccurate, but the
+    // connected directly to the IPO Clock node.  This is most likely inaccurate, but the
     // register description for MXC_GCR->pclkdiv marks the usual SDHC divider as reserved.
     // We will follow figure 4-1 for now.
 
     if (MXC_GCR->pclkdiv & MXC_F_GCR_PCLKDIS1_SDHC) {
-        return SystemCoreClock >> 2; // Div by 4
+        return IPO_FREQ >> 2; // Div by 4
     } else {
-        return SystemCoreClock >> 1; // Div by 2
+        return IPO_FREQ >> 1; // Div by 2
     }
 
-    return SystemCoreClock;
+    return IPO_FREQ;
 }
 
 /* ************************************************************************** */

Libraries/PeriphDrivers/Source/SDHC/sdhc_me10.c

@@ -85,9 +85,9 @@ unsigned int MXC_SDHC_Get_Clock_Config(void)
 unsigned int MXC_SDHC_Get_Input_Clock_Freq(void)
 {
     if (MXC_GCR->pclk_div & MXC_F_GCR_PCLK_DIV_SDHCFRQ) {
-        return SystemCoreClock >> 1; // Div by 2
+        return HIRC120_FREQ >> 1; // Div by 2
     } else {
-        return 50000000; // UG specifies a hard-coded 50Mhz value in this case
+        return CRYPTO_FREQ_A3; // UG specifies a hard-coded 50Mhz low-power oscillator
     }
 }
 

Libraries/PeriphDrivers/Source/SDHC/sdhc_me13.c

@@ -68,9 +68,9 @@ unsigned int MXC_SDHC_Get_Input_Clock_Freq(void)
 {
     // TODO(JC): Confirm this is the scheme used by ME13
     if (MXC_GCR->pclkdiv & MXC_F_GCR_PCLKDIV_SDHCFRQ) {
-        return SystemCoreClock >> 2; // Div by 4
+        return IPO_FREQ >> 2; // Div by 4
     } else {
-        return SystemCoreClock >> 1; // Div by 2
+        return IPO_FREQ >> 1; // Div by 2
     }
 }