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fix(CMSIS): Remove UART PIN register from MAX32657 #1318

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merged 1 commit into from
Jan 7, 2025
Merged

fix(CMSIS): Remove UART PIN register from MAX32657 #1318

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20 changes: 0 additions & 20 deletions Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd
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Original file line number Diff line number Diff line change
Expand Up @@ -10928,26 +10928,6 @@
</field>
</fields>
</register>
<register>
<name>PIN</name>
<description> Pin register</description>
<addressOffset>0x001C</addressOffset>
<fields>
<field>
<name>CTS</name>
<description>Current sampled value of CTS IO</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RTS</name>
<description>This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FIFO</name>
<description>FIFO Read/Write register</description>
Expand Down
17 changes: 1 addition & 16 deletions Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h
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Expand Up @@ -83,7 +83,7 @@ typedef struct {
__IO uint32_t clkdiv; /**< <tt>\b 0x0010:</tt> UART CLKDIV Register */
__IO uint32_t osr; /**< <tt>\b 0x0014:</tt> UART OSR Register */
__IO uint32_t txpeek; /**< <tt>\b 0x0018:</tt> UART TXPEEK Register */
__IO uint32_t pin; /**< <tt>\b 0x001C:</tt> UART PIN Register */
__R uint32_t rsv_0x1c;
__IO uint32_t fifo; /**< <tt>\b 0x0020:</tt> UART FIFO Register */
__R uint32_t rsv_0x24_0x2f[3];
__IO uint32_t dma; /**< <tt>\b 0x0030:</tt> UART DMA Register */
Expand All @@ -105,7 +105,6 @@ typedef struct {
#define MXC_R_UART_CLKDIV ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */
#define MXC_R_UART_OSR ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */
#define MXC_R_UART_TXPEEK ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */
#define MXC_R_UART_PIN ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */
#define MXC_R_UART_FIFO ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */
#define MXC_R_UART_DMA ((uint32_t)0x00000030UL) /**< Offset from UART Base Address: <tt> 0x0030</tt> */
#define MXC_R_UART_WKEN ((uint32_t)0x00000034UL) /**< Offset from UART Base Address: <tt> 0x0034</tt> */
Expand Down Expand Up @@ -306,20 +305,6 @@ typedef struct {

/**@} end of group UART_TXPEEK_Register */

/**
* @ingroup uart_registers
* @defgroup UART_PIN UART_PIN
* @brief Pin register
* @{
*/
#define MXC_F_UART_PIN_CTS_POS 0 /**< PIN_CTS Position */
#define MXC_F_UART_PIN_CTS ((uint32_t)(0x1UL << MXC_F_UART_PIN_CTS_POS)) /**< PIN_CTS Mask */

#define MXC_F_UART_PIN_RTS_POS 1 /**< PIN_RTS Position */
#define MXC_F_UART_PIN_RTS ((uint32_t)(0x1UL << MXC_F_UART_PIN_RTS_POS)) /**< PIN_RTS Mask */

/**@} end of group UART_PIN_Register */

/**
* @ingroup uart_registers
* @defgroup UART_FIFO UART_FIFO
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20 changes: 0 additions & 20 deletions Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd
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Original file line number Diff line number Diff line change
Expand Up @@ -346,26 +346,6 @@
</field>
</fields>
</register>
<register>
<name>PIN</name>
<description> Pin register</description>
<addressOffset>0x001C</addressOffset>
<fields>
<field>
<name>CTS</name>
<description>Current sampled value of CTS IO</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RTS</name>
<description>This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FIFO</name>
<description>FIFO Read/Write register</description>
Expand Down
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