VEXConverter: Convert DirtyStmts to Assignments. (#240)

* VEXConverter: Convert DirtyStmts to Assignments.

* Lint code.

* Handle invalid tmps.

ailment/converter_vex.py

@@ -1,3 +1,4 @@
+# pylint:disable=missing-class-docstring
 import logging
 
 import pyvex
@@ -628,6 +629,32 @@ def CAS(idx, stmt: pyvex.IRStmt.CAS, manager):
 
         return stmts
 
+    @staticmethod
+    def Dirty(idx, stmt: pyvex.IRStmt.Dirty, manager):
+        # we translate it into tmp = DirtyExpression() if possible
+
+        if stmt.tmp == 0xFFFFFFFF:
+            return DirtyStatement(
+                idx,
+                stmt,
+                ins_addr=manager.ins_addr,
+                vex_block_addr=manager.block_addr,
+                vex_stmt_idx=manager.vex_stmt_idx,
+            )
+
+        bits = manager.tyenv.sizeof(stmt.tmp)
+        tmp = VEXExprConverter.tmp(stmt.tmp, bits, manager)
+        dirty_expr = DirtyExpression(manager.next_atom(), stmt, bits=bits)
+
+        return Assignment(
+            idx,
+            tmp,
+            dirty_expr,
+            ins_addr=manager.ins_addr,
+            vex_block_addr=manager.block_addr,
+            vex_stmt_idx=manager.vex_stmt_idx,
+        )
+
 
 STATEMENT_MAPPINGS = {
     pyvex.IRStmt.Put: VEXStmtConverter.Put,
@@ -637,6 +664,7 @@ def CAS(idx, stmt: pyvex.IRStmt.CAS, manager):
     pyvex.IRStmt.StoreG: VEXStmtConverter.StoreG,
     pyvex.IRStmt.LoadG: VEXStmtConverter.LoadG,
     pyvex.IRStmt.CAS: VEXStmtConverter.CAS,
+    pyvex.IRStmt.Dirty: VEXStmtConverter.Dirty,
 }