[SOL] Split features into SBF versions

llvm/include/llvm/BinaryFormat/ELF.h

@@ -895,7 +895,10 @@ enum : unsigned {
 
 // SBF specific e_flags
 enum : unsigned {
-  EF_SBF_V2 = 0x20,
+  EF_SBF_V0 = 0x00,
+  EF_SBF_V1 = 0x01,
+  EF_SBF_V2 = 0x02,
+  EF_SBF_V3 = 0x03,
 };
 
 // ELF Relocation types for SBF.

llvm/lib/Target/SBF/MCTargetDesc/SBFAsmBackend.cpp

@@ -26,7 +26,6 @@ class SBFAsmBackend : public MCAsmBackend {
 public:
   SBFAsmBackend(endianness Endian, const MCSubtargetInfo &STI)
       : MCAsmBackend(Endian),
-        isSBFv2(STI.getCPU() == "sbfv2"),
         relocAbs64(STI.hasFeature(SBF::FeatureRelocAbs64)) {}
   ~SBFAsmBackend() override = default;
 
@@ -50,7 +49,6 @@ class SBFAsmBackend : public MCAsmBackend {
   bool writeNopData(raw_ostream &OS, uint64_t Count,
                     const MCSubtargetInfo *STI) const override;
 private:
-  bool isSBFv2;
   bool relocAbs64;
 };
 
@@ -107,7 +105,7 @@ void SBFAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
 
 std::unique_ptr<MCObjectTargetWriter>
 SBFAsmBackend::createObjectTargetWriter() const {
-  return createSBFELFObjectWriter(0, relocAbs64, isSBFv2);
+  return createSBFELFObjectWriter(0, relocAbs64);
 }
 
 MCAsmBackend *llvm::createSBFAsmBackend(const Target &T,

llvm/lib/Target/SBF/MCTargetDesc/SBFELFObjectWriter.cpp

@@ -22,7 +22,7 @@ namespace {
 
 class SBFELFObjectWriter : public MCELFObjectTargetWriter {
 public:
-  SBFELFObjectWriter(uint8_t OSABI, bool relocAbs64, bool isSBFv2);
+  SBFELFObjectWriter(uint8_t OSABI, bool relocAbs64);
   ~SBFELFObjectWriter() override = default;
 
 protected:
@@ -47,10 +47,8 @@ bool SBFELFObjectWriter::needsRelocateWithSymbol(const MCValue &Val,
   return true;
 }
 
-SBFELFObjectWriter::SBFELFObjectWriter(uint8_t OSABI,
-                                       bool relocAbs64, bool isSBFv2)
-  : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI,
-                            isSBFv2 ? ELF::EM_SBF : ELF::EM_BPF,
+SBFELFObjectWriter::SBFELFObjectWriter(uint8_t OSABI, bool relocAbs64)
+  : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI,ELF::EM_SBF,
                             /*HasRelocationAddend*/ false),
       relocAbs64(relocAbs64) {}
 
@@ -110,6 +108,6 @@ unsigned SBFELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
 }
 
 std::unique_ptr<MCObjectTargetWriter>
-llvm::createSBFELFObjectWriter(uint8_t OSABI, bool useRelocAbs64, bool isSBFv2) {
-  return std::make_unique<SBFELFObjectWriter>(OSABI, useRelocAbs64, isSBFv2);
+llvm::createSBFELFObjectWriter(uint8_t OSABI, bool useRelocAbs64) {
+  return std::make_unique<SBFELFObjectWriter>(OSABI, useRelocAbs64);
 }

llvm/lib/Target/SBF/MCTargetDesc/SBFMCTargetDesc.cpp

@@ -67,9 +67,18 @@ static MCStreamer *createSBFMCStreamer(const Triple &T, MCContext &Ctx,
   if (RelaxAll)
     S->getAssembler().setRelaxAll(true);
   const MCSubtargetInfo *STI = Ctx.getSubtargetInfo();
-  if (STI->getCPU() == "sbfv2") {
-    S->getAssembler().setELFHeaderEFlags(llvm::ELF::EF_SBF_V2);
+
+  StringRef CPU = STI->getCPU();
+  unsigned EFlag = llvm::ELF::EF_SBF_V0;
+  if (CPU == "v1") {
+    EFlag = llvm::ELF::EF_SBF_V1;
+  } else if (CPU == "v2") {
+    EFlag = llvm::ELF::EF_SBF_V2;
+  } else if (CPU == "v3") {
+    EFlag = llvm::ELF::EF_SBF_V3;
   }
+  S->getAssembler().setELFHeaderEFlags(EFlag);
+
   return S;
 }
 

llvm/lib/Target/SBF/MCTargetDesc/SBFMCTargetDesc.h

@@ -43,7 +43,7 @@ MCAsmBackend *createSBFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI,
                                     const MCTargetOptions &Options);
 
 std::unique_ptr<MCObjectTargetWriter>
-createSBFELFObjectWriter(uint8_t OSABI, bool useRelocAbs64, bool isSBFv2);
+createSBFELFObjectWriter(uint8_t OSABI, bool useRelocAbs64);
 } // namespace llvm
 
 // Defines symbolic names for SBF registers.  This defines a mapping from

llvm/lib/Target/SBF/SBFSubtarget.cpp

@@ -36,10 +36,10 @@ SBFSubtarget &SBFSubtarget::initializeSubtargetDependencies(const Triple &TT,
 
 void SBFSubtarget::initializeEnvironment(const Triple &TT) {
   assert(TT.getArch() == Triple::sbf && "expected Triple::sbf");
-  HasJmpExt = false;
   UseDwarfRIS = false;
 
   // SBFv2 features
+  HasJmpExt = false;
   HasDynamicFrames = false;
   DisableNeg = false;
   ReverseSubImm = false;
@@ -50,24 +50,11 @@ void SBFSubtarget::initializeEnvironment(const Triple &TT) {
   HasAlu32 = false;
   HasExplicitSignExt = false;
   NewMemEncoding = false;
+  HasStaticSyscalls = false;
 }
 
 void SBFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
-
-  if (CPU == "v2") {
-    HasJmpExt = true;
-  }
-
-  if (CPU == "v3") {
-    HasJmpExt = true;
-    HasAlu32 = true;
-  }
-
-  if (CPU == "sbfv2") {
-    if (!HasDynamicFrames)
-      report_fatal_error("sbfv2 requires dynamic-frames\n", false);
-  }
 }
 
 SBFSubtarget::SBFSubtarget(const Triple &TT, const std::string &CPU,

llvm/lib/Target/SBF/SBFTargetFeatures.td

@@ -49,13 +49,18 @@ def FeatureExplicitSext : SubtargetFeature<"explicit-sext", "HasExplicitSignExt"
 def FeatureNewMemEncoding : SubtargetFeature<"mem-encoding", "NewMemEncoding",
                                        "true", "Enable the new encoding for memory instructions">;
 
+def FeatureJumpExt : SubtargetFeature<"jmp-ext", "HasJmpExt",
+                                       "true", "Enable jumps with less than and less than or equal">;
+
 class Proc<string Name, list<SubtargetFeature> Features>
  : Processor<Name, NoItineraries, Features>;
 
 def : Proc<"generic", []>;
-def : Proc<"v1", []>;
-def : Proc<"v2", []>;
-def : Proc<"v3", [ALU32]>;
-def : Proc<"sbfv2", [FeatureDynamicFrames, FeatureRelocAbs64, FeatureStaticSyscalls,
-                        FeatureDisableNeg, FeatureReverseSubImm, FeatureDisableLddw, FeatureCallxRegSrc,
-                          FeaturePqrInstr, FeatureExplicitSext]>;
+
+def : Proc<"v1", [FeatureDynamicFrames, FeatureStoreImm, FeatureJumpExt]>;
+def : Proc<"v2", [FeatureDynamicFrames, FeatureStoreImm, FeatureJumpExt, FeatureDisableLddw,
+                  FeatureNewMemEncoding, FeatureCallxRegSrc, FeaturePqrInstr, FeatureExplicitSext,
+                  FeatureDisableNeg, FeatureReverseSubImm, ALU32]>;
+def : Proc<"v3", [FeatureDynamicFrames, FeatureStoreImm, FeatureJumpExt, FeatureDisableLddw,
+                  FeatureNewMemEncoding, FeatureCallxRegSrc, FeaturePqrInstr, FeatureExplicitSext,
+                  FeatureDisableNeg, FeatureReverseSubImm, ALU32, FeatureStaticSyscalls, FeatureRelocAbs64]>;

llvm/test/CodeGen/SBF/32-bit-subreg-alu.ll

@@ -1,5 +1,5 @@
-; RUN: llc -O2 -march=sbf -mattr=+alu32 < %s | FileCheck %s
-; RUN: llc -O2 -march=sbf -mcpu=v3 < %s | FileCheck %s
+; RUN: llc -O2 -march=sbf -mattr=+alu32 < %s | FileCheck --check-prefixes=CHECK,CHECK-V0 %s
+; RUN: llc -O2 -march=sbf -mcpu=v3 < %s | FileCheck --check-prefixes=CHECK,CHECK-V3 %s
 ;
 ; int mov(int a)
 ; {
@@ -130,7 +130,8 @@
 define dso_local i32 @mov(i32 returned %a) local_unnamed_addr #0 {
 entry:
   ret i32 %a
-; CHECK: mov32 w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK-V0: mov32 w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK-V3: mov64 w{{[0-9]+}}, w{{[0-9]+}}
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -208,15 +209,17 @@ entry:
 define dso_local i32 @rem(i32 %a, i32 %b) local_unnamed_addr #0 {
 entry:
   %rem = urem i32 %a, %b
-; CHECK: mod32 w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK-V0: mod32 w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK-V3: urem32 w{{[0-9]+}}, w{{[0-9]+}}
   ret i32 %rem
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define dso_local i32 @rem_i(i32 %a) local_unnamed_addr #0 {
 entry:
   %rem = urem i32 %a, 15
-; CHECK: mod32 w{{[0-9]+}}, 15
+; CHECK-V0: mod32 w{{[0-9]+}}, 15
+; CHECK-V3: urem32 w{{[0-9]+}}, 15
   ret i32 %rem
 }
 
@@ -320,6 +323,7 @@ entry:
 define dso_local i32 @neg(i32 %a) local_unnamed_addr #0 {
 entry:
   %sub = sub nsw i32 0, %a
-; CHECK: mov32 w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK-V0: mov32 w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK-V3: mov64 w{{[0-9]+}}, w{{[0-9]+}}
   ret i32 %sub
 }

llvm/test/CodeGen/SBF/32-bit-subreg-peephole.ll

@@ -1,4 +1,4 @@
-; RUN: llc -O2 -march=sbf -mcpu=v2 -mattr=+alu32 < %s | FileCheck %s
+; RUN: llc -O2 -march=sbf -mcpu=v2 < %s | FileCheck %s
 ;
 ; long long select_u(unsigned a, unsigned b, long long c, long long d)
 ; {
@@ -47,7 +47,7 @@ define dso_local i64 @select_u(i32 %a, i32 %b, i64 %c, i64 %d) local_unnamed_add
 entry:
   %cmp = icmp ugt i32 %a, %b
   %c.d = select i1 %cmp, i64 %c, i64 %d
-; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}}
+; CHECK: mov64 r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK-NOT: lsh32 r{{[0-9]+}}, 32
 ; CHECK-NOT: rsh32 r{{[0-9]+}}, 32
 ; CHECK: {{jlt|jgt}}  r{{[0-9]+}}, r{{[0-9]+}},
@@ -59,7 +59,7 @@ define dso_local i64 @select_u_2(i32 %a, i64 %b, i64 %c, i64 %d) local_unnamed_a
 ; CHECK-LABEL: select_u_2:
 entry:
   %conv = zext i32 %a to i64
-; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}}
+; CHECK: mov64 r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK-NOT: lsh32 r{{[0-9]+}}, 32
 ; CHECK-NOT: rsh32 r{{[0-9]+}}, 32
   %cmp = icmp ugt i64 %conv, %b
@@ -73,8 +73,8 @@ define dso_local i64 @select_s(i32 %a, i32 %b, i64 %c, i64 %d) local_unnamed_add
 entry:
   %cmp = icmp sgt i32 %a, %b
   %c.d = select i1 %cmp, i64 %c, i64 %d
-; CHECK: lsh64 r{{[0-9]+}}, 32
-; CHECK-NEXT: arsh64 r{{[0-9]+}}, 32
+; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}}
+; CHECK-NEXT: mov32 r{{[0-9]+}}, w{{[0-9]+}}
 ; CHECK: {{jslt|jsgt}} r{{[0-9]+}}, r{{[0-9]+}},
   ret i64 %c.d
 }
@@ -88,11 +88,12 @@ entry:
   %cmp = icmp ult i32 %conv, 10
 ; %call comes from function call returning i64 so the high bits will need
 ; to be cleared.
-; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}}
+; CHECK: and32 w{{[0-9]+}}, -1
 ; CHECK-NOT: lsh32 r{{[0-9]+}}, 32
 ; CHECK-NOT: rsh32 r{{[0-9]+}}, 32
+; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}}
   %b.c = select i1 %cmp, i32 %b, i32 %c
-; CHECK: {{jlt|jgt}} r{{[0-9]+}}, {{[0-9]+}},
+; CHECK: {{jlt|jgt}} r{{[0-9]+}}, 10,
   ret i32 %b.c
 }
 
@@ -103,7 +104,7 @@ define dso_local i32* @inc_p(i32* readnone %p, i32 %a) local_unnamed_addr #0 {
 ; CHECK-LABEL: inc_p:
 entry:
   %idx.ext = zext i32 %a to i64
-; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}}
+; CHECK: mov64 r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK-NOT: lsh32 r{{[0-9]+}}, 32
 ; CHECK-NOT: rsh32 r{{[0-9]+}}, 32
   %add.ptr = getelementptr inbounds i32, i32* %p, i64 %idx.ext
@@ -117,8 +118,8 @@ entry:
   %cmp = icmp sgt i32 %call, 6
 ; The shifts can't be optimized out because %call comes from function call
 ; return i32 so the high bits might be invalid.
-; CHECK: lsh64 r{{[0-9]+}}, 32
-; CHECK-NEXT: arsh64 r{{[0-9]+}}, 32
+; CHECK: mov64 w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK: mov32 r{{[0-9]+}}, w{{[0-9]+}}
   %cond = zext i1 %cmp to i32
 ; CHECK: {{jslt|jsgt}} r{{[0-9]+}}, {{[0-9]+}},
   ret i32 %cond

llvm/test/CodeGen/SBF/CORE/simplifypatable-nullptr.ll

@@ -41,7 +41,7 @@ entry:
   br i1 %tobool.not, label %if.end, label %cleanup, !dbg !42
 
 ; CHECK-LABEL: test
-; CHECK:       ldxdw r1, [r1 + 8]
+; CHECK:       ldxdw r1, [r1 + 0]
 ; CHECK:       jne r1, 0,
 
 if.end:                                           ; preds = %entry
@@ -53,7 +53,8 @@ if.end:                                           ; preds = %entry
   %tobool1.not = icmp eq ptr %7, null, !dbg !46
   br i1 %tobool1.not, label %if.then2, label %cleanup, !dbg !48
 
-; CHECK:       mov64 r1, 8
+; CHECK:       mov32 r1,
+; CHECK:       hor64 r1,
 ; CHECK:       ldxdw r1, [r1 + 0]
 ; CHECK:       jne r1, 0,
 

llvm/test/CodeGen/SBF/call_internal.ll

@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=sbf --show-mc-encoding | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-V0 %s
 ; RUN: llc -march=sbf --filetype=obj -o - %s | llvm-objdump -d - | FileCheck --check-prefixes=CHECK-OBJ,CHECK-OBJ-V0 %s
-; RUN: llc < %s -march=sbf -mcpu=sbfv2 --show-mc-encoding | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-V3 %s
-; RUN: llc -march=sbf -mcpu=sbfv2 --filetype=obj -o - %s | llvm-objdump -d -
+; RUN: llc < %s -march=sbf -mcpu=v3 --show-mc-encoding | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-V3 %s
+; RUN: llc -march=sbf -mcpu=v3 --filetype=obj -o - %s | llvm-objdump -d -
 ;                                       | FileCheck --check-prefixes=CHECK-OBJ,CHECK-OBJ-V3 %s
 
 @.str = private unnamed_addr constant [5 x i8] c"foo\0A\00", align 1

llvm/test/CodeGen/SBF/callx.ll

@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=sbf --show-mc-encoding \
-; RUN:      | FileCheck %s -check-prefixes=CHECK-v1
-; RUN: llc < %s -march=sbf --mcpu=sbfv2 --show-mc-encoding \
+; RUN:      | FileCheck %s -check-prefixes=CHECK-v0
+; RUN: llc < %s -march=sbf --mcpu=v2 --show-mc-encoding \
 ; RUN:      | FileCheck %s -check-prefixes=CHECK-v2
 ; source:
 ;   int test(int (*f)(void)) { return f(); }
@@ -9,7 +9,7 @@
 define dso_local i32 @test(i32 ()* nocapture %f) local_unnamed_addr #0 {
 entry:
   %call = tail call i32 %f() #1
-; CHECK-v1: callx r{{[0-9]+}} # encoding: [0x8d,0x00,0x00,0x00,0x0{{[0-9]|a|b}},0x00,0x00,0x00]
+; CHECK-v0: callx r{{[0-9]+}} # encoding: [0x8d,0x00,0x00,0x00,0x0{{[0-9]|a|b}},0x00,0x00,0x00]
 ; CHECK-v2: callx r{{[0-9]+}} # encoding: [0x8d,0x{{[0-9]}}0,0x00,0x00,0x00,0x00,0x00,0x00]
   ret i32 %call
 }