xtensa: remove up_set_current_regs/up_current_regs #14960

hujun260 · 2024-11-26T13:45:22Z

Summary

reason:
up_set_current_regs initially had two functions:

1: To mark the entry into an interrupt state.
2: To record the context before an interrupt/exception. If we switch to a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs).

Currently, we record the context in other ways, so the second function is obsolete. Therefore, we need to rename up_set_current_regs to better reflect its actual meaning, which is solely to mark an interrupt.

Impact

xteansa

Testing

ci ostest

nuttxpr · 2024-11-26T13:57:47Z

[Experimental Bot, please feedback here]

This PR appears to partially meet the NuttX requirements. While it provides a reason for the change, it lacks crucial details.

Missing Information:

Summary:
- What functional part of the code is being changed? (e.g., specific files, functions, modules)
- How exactly does the renaming work? What is the new name? Just stating "rename" doesn't explain the implementation.
- Links to related NuttX issues are missing.
Impact: "xteansa" is not a valid answer. Each impact item (user, build, hardware, documentation, security, compatibility) requires a "YES/NO" followed by a description if the answer is "YES". The PR needs to clearly address the impact of this renaming on each of these areas. Consider even seemingly trivial impacts. For example, does this rename affect any public APIs?
Testing: "ci ostest" is insufficient. Provide details about the build host and target environments. The testing logs sections are empty; include actual logs demonstrating the functionality before and after the change. How do the logs prove the change works as intended? What specific tests were run?

Example of Improvements:

Summary:
Reason: The function up_set_current_regs originally served two purposes: marking interrupt entry and saving the current context. The context saving functionality is now handled elsewhere, rendering the latter purpose obsolete. This PR renames up_set_current_regs to up_enter_interrupt to accurately reflect its sole remaining function: marking interrupt entry. This change modifies the arch/cpu/context_switch.c file. (Replace with the actual file). No related NuttX issues.

Impact:

Impact on user: NO
Impact on build: NO
Impact on hardware: NO
Impact on documentation: YES. The documentation for the affected function will be updated to reflect the name change and the removal of the obsolete functionality. (Specify where the documentation is located)
Impact on security: NO
Impact on compatibility: YES (Potentially). If any out-of-tree code directly calls up_set_current_regs, it will need to be adapted to use up_enter_interrupt.
Anything else to consider: None.

Testing:

Build Host: Linux (Ubuntu 20.04), x86_64, GCC 9.4.0
Target: sim:qemu-x86_64

Testing logs before change:

(Show output of a test demonstrating the current behavior of up_set_current_regs)

Testing logs after change:

(Show output of the same test demonstrating the equivalent behavior with up_enter_interrupt.  Highlight any differences and explain why they demonstrate the fix.)

By providing this level of detail, the PR will be much easier to review and understand. It demonstrates a clear understanding of the change and its implications.

arch/xtensa/src/common/xtensa.h

arch/xtensa/src/common/xtensa_backtrace.c

tmedicci · 2024-11-27T13:19:47Z

I'll trigger our internal CI. Please wait it to merge it.

tmedicci · 2024-11-27T16:55:10Z

I'll trigger our internal CI. Please wait it to merge it.

We've found an issue with the backtrace dump feature applied to this PR. The backtrace for the task's assertion does not work as expected with our test application (please check below) when CONFIG_ARCH_INTERRUPTSTACK=0. In order to test it, build the following application for ESP32, ESP32-S2 or ESP32-S3 (using nsh) with the following configs:

CONFIG_ARCH_INTERRUPTSTACK=0
CONFIG_INIT_STACKSIZE=3072
CONFIG_ESPAPPS_BACKTRACE=y
CONFIG_SYSTEM_DUMPSTACK=y
CONFIG_SCHED_BACKTRACE=y
CONFIG_ALLSYMS=y

and then, run backtrace task:

nsh> backtrace task
The following instruction will cause an exception that will trigxtensa_user_panic: User Exception: EXCCAUSE=001d task: backtrace
dump_assert_info: Current Version: NuttX  10.4.0 995a3fc00e Nov 27 2024 13:43:27 xtensa
dump_assert_info: Assertion failed user panic: at file: :0 task: backtrace process: backtrace 0x400f0ae0
up_dump_register:    PC: 400f0b08    PS: 00060730
up_dump_register:    A0: 800e2e97    A1: 3ffe1400    A2: 00000000    A3: 3ffe0470
up_dump_register:    A4: 3ffe0486    A5: 3ffaf450    A6: 00000000    A7: 00000000
up_dump_register:    A8: 800f0b05    A9: 3ffe13d0   A10: 0000005a   A11: 3ffafcd8
up_dump_register:   A12: 00000059   A13: 3ffaf5a0   A14: 00000002   A15: 3ffafac8
up_dump_register:   SAR: 00000018 CAUSE: 0000001d VADDR: 00000000
up_dump_register:  LBEG: 4000c28c  LEND: 4000c296  LCNT: 00000000
dump_stackinfo: User Stack:
dump_stackinfo:   base: 0x3ffe0490
dump_stackinfo:   size: 00004048
dump_stackinfo:     sp: 0x3ffe1400
stack_dump: 0x3ffe13e0: 00000059 3ffaf5a0 00000002 3ffafac8 800e1de3 3ffe1420 400f0ae0 00000002
stack_dump: 0x3ffe1400: 3ffe0486 3ffaf450 00000000 00000000 00000000 3ffe1440 00000000 400f0ae0
stack_dump: 0x3ffe1420: 3ffe0470 3ffb1da4 00000000 3ffb0d2c 00000000 3ffe1460 00000000 00000000
stack_dump: 0x3ffe1440: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
stack_dump: 0x3ffe1460: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
xtensa_user_panic: User Exception: EXCCAUSE=001c task: backtrace

The test application:

/****************************************************************************
 * Copyright 2021 Espressif Systems (Shanghai) CO LTD
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ****************************************************************************/

/****************************************************************************
 * Included Files
 ****************************************************************************/

#include <nuttx/config.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/board/board.h>

#if defined(CONFIG_ARCH_CHIP_ESP32)
#  include "esp32_irq.h"
#  include "hardware/esp32_dport.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#  include "esp32s2_irq.h"
#  include "hardware/esp32s2_system.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
#  include "esp32s3_irq.h"
#  include "hardware/esp32s3_system.h"
#elif defined (CONFIG_ARCH_CHIP_ESP32C3_GENERIC)
#  include "espressif/esp_irq.h"
#  include "riscv/interrupt.h"
#  include "soc/system_reg.h"
#elif defined (CONFIG_ARCH_CHIP_ESP32C6) \
   || defined (CONFIG_ARCH_CHIP_ESP32H2)
#  include "espressif/esp_irq.h"
#  include "riscv/interrupt.h"
#  include "soc/intpri_reg.h"
#else
#  error "Unsupported Espressif SoC"
#endif

#if defined(CONFIG_ARCH_XTENSA)
#  include "xtensa.h"
#  include "xtensa_attr.h"
#else
#  include "riscv_internal.h"
#endif

/****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/

#if defined(CONFIG_ARCH_CHIP_ESP32)
#  define SETUP_IRQ(cpu, periphid, priority, type) esp32_setup_irq(cpu, periphid, priority, type)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#  define SETUP_IRQ(cpu, periphid, priority, type) esp32s2_setup_irq(periphid, priority, type)
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
#  define SETUP_IRQ(cpu, periphid, priority, type) esp32s3_setup_irq(cpu, periphid, priority, type)
#elif defined (CONFIG_ARCH_CHIP_ESP32C3_GENERIC) \
   || defined (CONFIG_ARCH_CHIP_ESP32C6) \
   || defined (CONFIG_ARCH_CHIP_ESP32H2)
#  define SETUP_IRQ(cpu, periphid, priority, type) esp_setup_irq(periphid, priority, type)
#else
#  error "Unsupported Espressif SoC"
#endif

/* Software Interrupt */

#if defined(CONFIG_ARCH_CHIP_ESP32)
#  define SWI_IRQ       ESP32_IRQ_CPU_CPU3
#  define SWI_PERIPH    ESP32_PERIPH_CPU_CPU3
#  define SWI_REG       DPORT_CPU_INTR_FROM_CPU_3_REG
#  define SWI_EN_BIT    DPORT_CPU_INTR_FROM_CPU_3
#  define SWI_TYPE      ESP32_CPUINT_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#  define SWI_IRQ       ESP32S2_IRQ_INT_FROM_CPU3
#  define SWI_PERIPH    ESP32S2_PERIPH_INT_FROM_CPU3
#  define SWI_REG       SYSTEM_CPU_INTR_FROM_CPU_3_REG
#  define SWI_EN_BIT    SYSTEM_CPU_INTR_FROM_CPU_3
#  define SWI_TYPE      ESP32S2_CPUINT_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
#  define SWI_IRQ       ESP32S3_IRQ_INT_FROM_CPU3
#  define SWI_PERIPH    ESP32S3_PERIPH_INT_FROM_CPU3
#  define SWI_REG       SYSTEM_CPU_INTR_FROM_CPU_3_REG
#  define SWI_EN_BIT    SYSTEM_CPU_INTR_FROM_CPU_3
#  define SWI_TYPE      ESP32S3_CPUINT_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32C3_GENERIC)
#  define SWI_IRQ       ESP_IRQ_FROM_CPU_INTR3
#  define SWI_PERIPH    FROM_CPU_INTR3_SOURCE
#  define SWI_REG       SYSTEM_CPU_INTR_FROM_CPU_3_REG
#  define SWI_EN_BIT    SYSTEM_CPU_INTR_FROM_CPU_3
#  define SWI_TYPE      INTR_TYPE_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32C6)
#  define SWI_IRQ       ESP_IRQ_FROM_CPU_INTR3
#  define SWI_PERIPH    FROM_CPU_INTR3_SOURCE
#  define SWI_REG       INTPRI_CPU_INTR_FROM_CPU_3_REG
#  define SWI_EN_BIT    INTPRI_CPU_INTR_FROM_CPU_3
#  define SWI_TYPE      INTR_TYPE_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32H2)
#  define SWI_IRQ       ESP_IRQ_FROM_CPU_INTR3
#  define SWI_PERIPH    FROM_CPU_INTR3_SOURCE
#  define SWI_REG       INTPRI_CPU_INTR_FROM_CPU_3_REG
#  define SWI_EN_BIT    INTPRI_CPU_INTR_FROM_CPU_3
#  define SWI_TYPE      INTR_TYPE_LEVEL
#else
#  error "Unsupported Espressif SoC"
#endif

/****************************************************************************
 * Private Types
 ****************************************************************************/

/****************************************************************************
 * Private Function Prototypes
 ****************************************************************************/

static void usage(const char *progname);
static void assert_on_task(void);
static int assert_on_interrupt_handler(int irq, void *context, void *arg);

/****************************************************************************
 * Private Data
 ****************************************************************************/

/****************************************************************************
 * Private Functions
 ****************************************************************************/

static void usage(const char *progname)
{
  printf("Usage: %s <test_type>\n", progname);
  printf("  test_type:\n");
  printf("    task    - Assert on task\n");
  printf("    irq     - Assert on interrupt handler\n");
}

static void assert_on_task(void)
{
  int *p = NULL;

  printf("The following instruction will cause an exception that will "
         "trigger a task backtrace dump\n");

  *p = 0;
}

static int assert_on_interrupt_handler(int irq, void *context, void *arg)
{
  int *p = NULL;

  modifyreg32(SWI_REG, SWI_EN_BIT, 0);

  *p = 0;

  return 0;
}

static void trigger_irq(void)
{

  /* Trigger the interrupt */

  modifyreg32(SWI_REG, 0, SWI_EN_BIT);
}

/****************************************************************************
 * Public Functions
 ****************************************************************************/

int main(int argc, char *argv[])
{
  if (argc != 2)
    {
      usage(argv[0]);
      return EXIT_FAILURE;
    }

  if (strcmp(argv[1], "task") == 0)
    {
      assert_on_task();
    }
  else if (strcmp(argv[1], "irq") == 0)
    {
      int priority = 1; /* Set appropriate priority */

      /* Setup the interrupt */
      int ret = SETUP_IRQ(0, SWI_PERIPH, priority, SWI_TYPE);
      if (ret < 0)
        {
          printf("Failed to setup IRQ: %d\n", ret);
          return EXIT_FAILURE;
        }

      /* Attach the interrupt handler */

      irq_attach(SWI_IRQ, assert_on_interrupt_handler, NULL);

      /* Enable the interrupt */

      up_enable_irq(SWI_IRQ);

      /* Trigger the interrupt */

      trigger_irq();
    }
  else
    {
      usage(argv[0]);
      return EXIT_FAILURE;
    }

  return EXIT_SUCCESS;
}

hujun260 · 2024-11-28T06:21:49Z

I'll trigger our internal CI. Please wait it to merge it.

We've found an issue with the backtrace dump feature applied to this PR. The backtrace for the task's assertion does not work as expected with our test application (please check below) when CONFIG_ARCH_INTERRUPTSTACK=0. In order to test it, build the following application for ESP32, ESP32-S2 or ESP32-S3 (using nsh) with the following configs:

CONFIG_ARCH_INTERRUPTSTACK=0
CONFIG_INIT_STACKSIZE=3072
CONFIG_ESPAPPS_BACKTRACE=y
CONFIG_SYSTEM_DUMPSTACK=y
CONFIG_SCHED_BACKTRACE=y
CONFIG_ALLSYMS=y

and then, run backtrace task:

nsh> backtrace task
The following instruction will cause an exception that will trigxtensa_user_panic: User Exception: EXCCAUSE=001d task: backtrace
dump_assert_info: Current Version: NuttX  10.4.0 995a3fc00e Nov 27 2024 13:43:27 xtensa
dump_assert_info: Assertion failed user panic: at file: :0 task: backtrace process: backtrace 0x400f0ae0
up_dump_register:    PC: 400f0b08    PS: 00060730
up_dump_register:    A0: 800e2e97    A1: 3ffe1400    A2: 00000000    A3: 3ffe0470
up_dump_register:    A4: 3ffe0486    A5: 3ffaf450    A6: 00000000    A7: 00000000
up_dump_register:    A8: 800f0b05    A9: 3ffe13d0   A10: 0000005a   A11: 3ffafcd8
up_dump_register:   A12: 00000059   A13: 3ffaf5a0   A14: 00000002   A15: 3ffafac8
up_dump_register:   SAR: 00000018 CAUSE: 0000001d VADDR: 00000000
up_dump_register:  LBEG: 4000c28c  LEND: 4000c296  LCNT: 00000000
dump_stackinfo: User Stack:
dump_stackinfo:   base: 0x3ffe0490
dump_stackinfo:   size: 00004048
dump_stackinfo:     sp: 0x3ffe1400
stack_dump: 0x3ffe13e0: 00000059 3ffaf5a0 00000002 3ffafac8 800e1de3 3ffe1420 400f0ae0 00000002
stack_dump: 0x3ffe1400: 3ffe0486 3ffaf450 00000000 00000000 00000000 3ffe1440 00000000 400f0ae0
stack_dump: 0x3ffe1420: 3ffe0470 3ffb1da4 00000000 3ffb0d2c 00000000 3ffe1460 00000000 00000000
stack_dump: 0x3ffe1440: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
stack_dump: 0x3ffe1460: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
xtensa_user_panic: User Exception: EXCCAUSE=001c task: backtrace

The test application:

/****************************************************************************
 * Copyright 2021 Espressif Systems (Shanghai) CO LTD
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ****************************************************************************/

/****************************************************************************
 * Included Files
 ****************************************************************************/

#include <nuttx/config.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/board/board.h>

#if defined(CONFIG_ARCH_CHIP_ESP32)
#  include "esp32_irq.h"
#  include "hardware/esp32_dport.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#  include "esp32s2_irq.h"
#  include "hardware/esp32s2_system.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
#  include "esp32s3_irq.h"
#  include "hardware/esp32s3_system.h"
#elif defined (CONFIG_ARCH_CHIP_ESP32C3_GENERIC)
#  include "espressif/esp_irq.h"
#  include "riscv/interrupt.h"
#  include "soc/system_reg.h"
#elif defined (CONFIG_ARCH_CHIP_ESP32C6) \
   || defined (CONFIG_ARCH_CHIP_ESP32H2)
#  include "espressif/esp_irq.h"
#  include "riscv/interrupt.h"
#  include "soc/intpri_reg.h"
#else
#  error "Unsupported Espressif SoC"
#endif

#if defined(CONFIG_ARCH_XTENSA)
#  include "xtensa.h"
#  include "xtensa_attr.h"
#else
#  include "riscv_internal.h"
#endif

/****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/

#if defined(CONFIG_ARCH_CHIP_ESP32)
#  define SETUP_IRQ(cpu, periphid, priority, type) esp32_setup_irq(cpu, periphid, priority, type)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#  define SETUP_IRQ(cpu, periphid, priority, type) esp32s2_setup_irq(periphid, priority, type)
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
#  define SETUP_IRQ(cpu, periphid, priority, type) esp32s3_setup_irq(cpu, periphid, priority, type)
#elif defined (CONFIG_ARCH_CHIP_ESP32C3_GENERIC) \
   || defined (CONFIG_ARCH_CHIP_ESP32C6) \
   || defined (CONFIG_ARCH_CHIP_ESP32H2)
#  define SETUP_IRQ(cpu, periphid, priority, type) esp_setup_irq(periphid, priority, type)
#else
#  error "Unsupported Espressif SoC"
#endif

/* Software Interrupt */

#if defined(CONFIG_ARCH_CHIP_ESP32)
#  define SWI_IRQ       ESP32_IRQ_CPU_CPU3
#  define SWI_PERIPH    ESP32_PERIPH_CPU_CPU3
#  define SWI_REG       DPORT_CPU_INTR_FROM_CPU_3_REG
#  define SWI_EN_BIT    DPORT_CPU_INTR_FROM_CPU_3
#  define SWI_TYPE      ESP32_CPUINT_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#  define SWI_IRQ       ESP32S2_IRQ_INT_FROM_CPU3
#  define SWI_PERIPH    ESP32S2_PERIPH_INT_FROM_CPU3
#  define SWI_REG       SYSTEM_CPU_INTR_FROM_CPU_3_REG
#  define SWI_EN_BIT    SYSTEM_CPU_INTR_FROM_CPU_3
#  define SWI_TYPE      ESP32S2_CPUINT_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
#  define SWI_IRQ       ESP32S3_IRQ_INT_FROM_CPU3
#  define SWI_PERIPH    ESP32S3_PERIPH_INT_FROM_CPU3
#  define SWI_REG       SYSTEM_CPU_INTR_FROM_CPU_3_REG
#  define SWI_EN_BIT    SYSTEM_CPU_INTR_FROM_CPU_3
#  define SWI_TYPE      ESP32S3_CPUINT_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32C3_GENERIC)
#  define SWI_IRQ       ESP_IRQ_FROM_CPU_INTR3
#  define SWI_PERIPH    FROM_CPU_INTR3_SOURCE
#  define SWI_REG       SYSTEM_CPU_INTR_FROM_CPU_3_REG
#  define SWI_EN_BIT    SYSTEM_CPU_INTR_FROM_CPU_3
#  define SWI_TYPE      INTR_TYPE_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32C6)
#  define SWI_IRQ       ESP_IRQ_FROM_CPU_INTR3
#  define SWI_PERIPH    FROM_CPU_INTR3_SOURCE
#  define SWI_REG       INTPRI_CPU_INTR_FROM_CPU_3_REG
#  define SWI_EN_BIT    INTPRI_CPU_INTR_FROM_CPU_3
#  define SWI_TYPE      INTR_TYPE_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32H2)
#  define SWI_IRQ       ESP_IRQ_FROM_CPU_INTR3
#  define SWI_PERIPH    FROM_CPU_INTR3_SOURCE
#  define SWI_REG       INTPRI_CPU_INTR_FROM_CPU_3_REG
#  define SWI_EN_BIT    INTPRI_CPU_INTR_FROM_CPU_3
#  define SWI_TYPE      INTR_TYPE_LEVEL
#else
#  error "Unsupported Espressif SoC"
#endif

/****************************************************************************
 * Private Types
 ****************************************************************************/

/****************************************************************************
 * Private Function Prototypes
 ****************************************************************************/

static void usage(const char *progname);
static void assert_on_task(void);
static int assert_on_interrupt_handler(int irq, void *context, void *arg);

/****************************************************************************
 * Private Data
 ****************************************************************************/

/****************************************************************************
 * Private Functions
 ****************************************************************************/

static void usage(const char *progname)
{
  printf("Usage: %s <test_type>\n", progname);
  printf("  test_type:\n");
  printf("    task    - Assert on task\n");
  printf("    irq     - Assert on interrupt handler\n");
}

static void assert_on_task(void)
{
  int *p = NULL;

  printf("The following instruction will cause an exception that will "
         "trigger a task backtrace dump\n");

  *p = 0;
}

static int assert_on_interrupt_handler(int irq, void *context, void *arg)
{
  int *p = NULL;

  modifyreg32(SWI_REG, SWI_EN_BIT, 0);

  *p = 0;

  return 0;
}

static void trigger_irq(void)
{

  /* Trigger the interrupt */

  modifyreg32(SWI_REG, 0, SWI_EN_BIT);
}

/****************************************************************************
 * Public Functions
 ****************************************************************************/

int main(int argc, char *argv[])
{
  if (argc != 2)
    {
      usage(argv[0]);
      return EXIT_FAILURE;
    }

  if (strcmp(argv[1], "task") == 0)
    {
      assert_on_task();
    }
  else if (strcmp(argv[1], "irq") == 0)
    {
      int priority = 1; /* Set appropriate priority */

      /* Setup the interrupt */
      int ret = SETUP_IRQ(0, SWI_PERIPH, priority, SWI_TYPE);
      if (ret < 0)
        {
          printf("Failed to setup IRQ: %d\n", ret);
          return EXIT_FAILURE;
        }

      /* Attach the interrupt handler */

      irq_attach(SWI_IRQ, assert_on_interrupt_handler, NULL);

      /* Enable the interrupt */

      up_enable_irq(SWI_IRQ);

      /* Trigger the interrupt */

      trigger_irq();
    }
  else
    {
      usage(argv[0]);
      return EXIT_FAILURE;
    }

  return EXIT_SUCCESS;
}

fixed
missing update running_task

tmedicci · 2024-11-28T11:45:38Z

fixed missing update running_task

Thanks. I'll trigger it again

tmedicci · 2024-11-28T13:36:53Z

fixed missing update running_task

Thanks. I'll trigger it again

Xtensa is failing to build with

common/xtensa_assert.c: In function 'xtensa_panic':
common/xtensa_assert.c:75:3: error: implicit declaration of function 'xtensa_set_interrupt_context'; did you mean 'up_set_interrupt_context'? [-Werror=implicit-function-declaration]
   75 |   xtensa_set_interrupt_context(true);
      |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
      |   up_set_interrupt_context
cc1: all warnings being treated as errors
make[1]: *** [Makefile:144: xtensa_assert.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [tools/LibTargets.mk:170: arch/xtensa/src/libarch.a] Error 2
make: *** Waiting for unfinished jobs....

reason: up_set_current_regs initially had two functions: 1: To mark the entry into an interrupt state. 2: To record the context before an interrupt/exception. If we switch to a new task, we need to store the upcoming context regs by calling up_set_current_regs(regs). Currently, we record the context in other ways, so the second function is obsolete. Therefore, we need to rename up_set_current_regs to better reflect its actual meaning, which is solely to mark an interrupt. Signed-off-by: hujun5 <[email protected]>

This commit fixes the regression from apache#14865 Signed-off-by: hujun5 <[email protected]>

xiaoxiang781216 · 2024-11-29T02:49:57Z

@tmedicci does this patch pass your internal ci?

hujun260 · 2024-11-29T04:20:00Z

fixed missing update running_task

Thanks. I'll trigger it again

Xtensa is failing to build with

common/xtensa_assert.c: In function 'xtensa_panic':
common/xtensa_assert.c:75:3: error: implicit declaration of function 'xtensa_set_interrupt_context'; did you mean 'up_set_interrupt_context'? [-Werror=implicit-function-declaration]
   75 |   xtensa_set_interrupt_context(true);
      |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
      |   up_set_interrupt_context
cc1: all warnings being treated as errors
make[1]: *** [Makefile:144: xtensa_assert.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [tools/LibTargets.mk:170: arch/xtensa/src/libarch.a] Error 2
make: *** Waiting for unfinished jobs....

fixed

tmedicci · 2024-11-29T13:02:49Z

@tmedicci does this patch pass your internal ci?

I've just tested it again. It's now passing all tests. Thanks!

github-actions bot added Arch: xtensa Issues related to the Xtensa architecture Size: S The size of the change in this PR is small labels Nov 26, 2024

hujun260 force-pushed the apache_32 branch from 26d50cd to 56aadf2 Compare November 26, 2024 13:46

acassis requested a review from tmedicci November 26, 2024 16:51

acassis approved these changes Nov 26, 2024

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xiaoxiang781216 reviewed Nov 26, 2024

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hujun260 force-pushed the apache_32 branch from 56aadf2 to 995a3fc Compare November 26, 2024 23:49

hujun260 force-pushed the apache_32 branch 2 times, most recently from cc984f4 to 73bd040 Compare November 28, 2024 06:21

hujun260 force-pushed the apache_32 branch from 73bd040 to 56c8d13 Compare November 28, 2024 09:15

hujun260 force-pushed the apache_32 branch from 56c8d13 to cbdcb21 Compare November 28, 2024 13:56

xiaoxiang781216 approved these changes Nov 29, 2024

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missing update running_task

2181de3

This commit fixes the regression from apache#14865 Signed-off-by: hujun5 <[email protected]>

hujun260 force-pushed the apache_32 branch from cbdcb21 to 2181de3 Compare November 29, 2024 01:14

xiaoxiang781216 approved these changes Nov 29, 2024

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xiaoxiang781216 merged commit 3214194 into apache:master Nov 29, 2024
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hujun260 deleted the apache_32 branch December 1, 2024 02:53

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xtensa: remove up_set_current_regs/up_current_regs #14960

xtensa: remove up_set_current_regs/up_current_regs #14960

hujun260 commented Nov 26, 2024

nuttxpr commented Nov 26, 2024

tmedicci commented Nov 27, 2024

tmedicci commented Nov 27, 2024

hujun260 commented Nov 28, 2024

tmedicci commented Nov 28, 2024

tmedicci commented Nov 28, 2024

xiaoxiang781216 commented Nov 29, 2024

hujun260 commented Nov 29, 2024

tmedicci commented Nov 29, 2024

xtensa: remove up_set_current_regs/up_current_regs #14960

xtensa: remove up_set_current_regs/up_current_regs #14960

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hujun260 commented Nov 26, 2024

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Testing

nuttxpr commented Nov 26, 2024

tmedicci commented Nov 27, 2024

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hujun260 commented Nov 28, 2024

tmedicci commented Nov 28, 2024

tmedicci commented Nov 28, 2024

xiaoxiang781216 commented Nov 29, 2024

hujun260 commented Nov 29, 2024

tmedicci commented Nov 29, 2024