riscv/riscv_ipi.h: Do not write to CSR_MIP.MSIP as it is read-only#14967
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xiaoxiang781216 merged 1 commit intoapache:masterfrom Nov 28, 2024
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riscv/riscv_ipi.h: Do not write to CSR_MIP.MSIP as it is read-only#14967xiaoxiang781216 merged 1 commit intoapache:masterfrom
xiaoxiang781216 merged 1 commit intoapache:masterfrom
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From the RISV-V Privileged Spec v1.10 (3.1.14 MIP/MIE): Only the bits corresponding to lower-privilege software interrupts (USIP, SSIP), timer interrupts (UTIP, STIP), and external interrupts (UEIP, SEIP) in mip are writable through this CSR address; the remaining bits are read-only. Thus, it is futile to write to the M-mode status bit via the CSR, only access via RISCV_IPI is valid.
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Summary
From the RISV-V Privileged Spec v1.10 (3.1.14 MIP/MIE):
Only the bits corresponding to lower-privilege software interrupts (USIP, SSIP), timer interrupts (UTIP, STIP), and external interrupts (UEIP, SEIP) in mip are writable through this CSR address; the remaining bits are read-only.
Thus, it is futile to write to the M-mode status bit via the CSR, only access via RISCV_IPI is valid.
Impact
RISC-V SMP only.
Testing
rv-virt:smp64
rv-virt:smp
rv-virt:ksmp64