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Added RISC-V V extension intrinsics for LLVM #18182

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Added RISC-V V extension intrinsics for LLVM #18182

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b558b12
Added RISC-V V extension intrinsics for LLVM
fzi-peccia Jun 26, 2025
918d22e
Added diff proposal to reuse target.llvm_get_vector_width
fzi-peccia Aug 18, 2025
49d9a0c
Fixes/changes based on comments on PR
fzi-peccia Aug 18, 2025
f9b2667
Lint fixes + call_llvm_intrin nargs change
fzi-peccia Aug 18, 2025
a86c214
Intrinsic registration mistakes fixed
fzi-peccia Aug 21, 2025
9f363b5
Enabled RVV intrinsics as experimental
fzi-peccia Aug 21, 2025
91592e9
Lint fixes
fzi-peccia Aug 21, 2025
10cf781
CI Lint fix
fzi-peccia Aug 22, 2025
c56e82d
CI fix
fzi-peccia Aug 22, 2025
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2 changes: 2 additions & 0 deletions include/tvm/meta_schedule/postproc.h
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Expand Up @@ -166,6 +166,8 @@ class Postproc : public runtime::ObjectRef {
TVM_DLL static Array<Postproc, void> DefaultLLVM();
/*! \brief Create default postprocessors for x86 (AVX512 and VNNI) */
TVM_DLL static Array<Postproc, void> DefaultCPUTensorization();
/*! \brief Create default postprocessors for RISCV */
TVM_DLL static Array<Postproc, void> DefaultRISCV();
/*! \brief Create default postprocessors for CUDA */
TVM_DLL static Array<Postproc, void> DefaultCUDA();
/*! \brief Create default postprocessors for CUDA with TensorCore */
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2 changes: 2 additions & 0 deletions include/tvm/meta_schedule/schedule_rule.h
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Expand Up @@ -301,6 +301,8 @@ class ScheduleRule : public runtime::ObjectRef {
TVM_DLL static Array<ScheduleRule, void> DefaultHexagon();
/*! \brief Create default schedule rules for ARM CPU (NEON and DOTPROD) */
TVM_DLL static Array<ScheduleRule, void> DefaultARM(const String& type);
/*! \brief Create default schedule rules for RISCV CPU (RVV) */
TVM_DLL static Array<ScheduleRule, void> DefaultRISCV(int vlen);

TVM_DEFINE_MUTABLE_OBJECT_REF_METHODS(ScheduleRule, ObjectRef, ScheduleRuleNode);
};
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8 changes: 8 additions & 0 deletions python/tvm/target/target.py
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Expand Up @@ -637,6 +637,14 @@ def riscv_cpu(model="sifive-u54", options=None):
"-mabi=lp64d",
# cc: riscv64-unknown-linux-gnu-g++ -march=rv64gc -mabi=lp64d -mcpu=sifive-u74
],
"bpi-f3": [
"-mtriple=riscv64-unknown-linux-gnu",
"-mcpu=generic",
"-mfloat-abi=hard",
"-num-cores=8",
"-mabi=lp64d",
"-mattr=+v,+zvl256b",
],
}
pre_defined_opt = trans_table.get(model, ["-model=%s" % model])

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2 changes: 1 addition & 1 deletion python/tvm/tir/tensor_intrin/__init__.py
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Expand Up @@ -20,4 +20,4 @@
from . import cuda

if enabled("llvm"):
from . import arm_cpu, x86, rocm, hexagon
from . import arm_cpu, x86, rocm, hexagon, riscv_cpu
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