update axerrno and page_table*, add comments, bump to 0.3.0 due to incompatible deps

Cargo.toml

@@ -11,7 +11,7 @@ keywords = ["hypervisor", "address-space"]
 license = "Apache-2.0"
 name = "axaddrspace"
 repository = "https://github.com/arceos-hypervisor/axaddrspace"
-version = "0.2.0"
+version = "0.3.0"
 
 [features]
 arm-el2 = ["page_table_entry/arm-el2"]
@@ -26,11 +26,11 @@ log = "0.4"
 numeric-enum-macro = "0.2"
 
 # Operating system independent modules provided by ArceOS.
-axerrno = "0.1.0"
+axerrno = "0.2.0"
 memory_addr = "0.4"
 memory_set = "0.4"
-page_table_entry = "0.5"
-page_table_multiarch = "0.5"
+page_table_entry = "0.6"
+page_table_multiarch = "0.6"
 
 [target.'cfg(any(target_arch = "x86_64", doc))'.dependencies]
 x86 = "0.52"
@@ -40,4 +40,3 @@ lazy_static = "1.5"
 spin = "0.10"
 assert_matches = "1.5.0"
 axin = "0.1.0"
-

src/address_space/mod.rs

@@ -15,7 +15,7 @@
 use alloc::vec::Vec;
 use core::fmt;
 
-use axerrno::ax_err;
+use axerrno::{AxResult, ax_err};
 use memory_addr::{MemoryAddr, PhysAddr, is_aligned_4k};
 use memory_set::{MemoryArea, MemorySet};
 use page_table_multiarch::PagingHandler;
@@ -25,7 +25,6 @@ use crate::{GuestPhysAddr, GuestPhysAddrRange, mapping_err_to_ax_err};
 
 mod backend;
 
-pub use axerrno::{AxError, AxResult};
 pub use backend::Backend;
 pub use page_table_entry::MappingFlags;
 

src/lib.rs

@@ -37,6 +37,7 @@ pub use hal::AxMmHal;
 
 pub use memory_accessor::GuestMemoryAccessor;
 
+use axerrno::AxError;
 use memory_set::MappingError;
 
 /// Information about nested page faults.

src/npt/mod.rs

@@ -23,13 +23,14 @@ use crate::GuestPhysAddr;
 cfg_if::cfg_if! {
     if #[cfg(target_arch = "x86_64")] {
         pub type NestedPageTableL4<H> = arch::ExtendedPageTable<H>;
-
     } else if #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] {
+        /// RISC-V Level 3 nested page table (Sv39, x4 not supported)
         pub type NestedPageTableL3<H> = page_table_multiarch::PageTable64<arch::Sv39MetaData<GuestPhysAddr>, arch::Rv64PTE, H>;
-        pub type NestedPageTableL4<H> = page_table_multiarch::PageTable64<arch::Sv48MetaData<GuestPhysAddr>, arch::Rv64PTE, H>;
 
+        /// RISC-V Level 4 nested page table (Sv48, x4 not supported)
+        pub type NestedPageTableL4<H> = page_table_multiarch::PageTable64<arch::Sv48MetaData<GuestPhysAddr>, arch::Rv64PTE, H>;
     } else if #[cfg(target_arch = "aarch64")] {
-       /// AArch64 Level 3 nested page table type alias.
+        /// AArch64 Level 3 nested page table type alias.
         pub type NestedPageTableL3<H> = page_table_multiarch::PageTable64<arch::A64HVPagingMetaDataL3, arch::A64PTEHV, H>;
 
         /// AArch64 Level 4 nested page table type alias.
@@ -69,7 +70,7 @@ impl<H: PagingHandler> NestedPageTable<H> {
         }
     }
 
-    pub fn root_paddr(&self) -> memory_addr::PhysAddr {
+    pub const fn root_paddr(&self) -> memory_addr::PhysAddr {
         match self {
             #[cfg(not(target_arch = "x86_64"))]
             NestedPageTable::L3(pt) => pt.root_paddr(),