Adapt to new dependencies, remove hal, bump version to v0.3.0

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "riscv_vcpu"
-version = "0.2.2"
+version = "0.3.0"
 edition = "2024"
 authors = [
     "KeYang Hu <keyang.hu@qq.com>",
@@ -23,7 +23,7 @@ log = "0.4"
 cfg-if = "1.0"
 bitflags = "2.2"
 bit_field = "0.10"
-crate_interface = "0.1"
+crate_interface = "0.3"
 
 riscv = { version = "0.14.0", features = ["s-mode"] }
 riscv-h = "0.2"
@@ -32,13 +32,13 @@ riscv-decode = "0.2.3"
 rustsbi = { version = "0.4.0", features = ["forward"] }
 sbi-rt = { version = "0.0.3", features = ["integer-impls"] }
 sbi-spec = { version = "0.0.7", features = ["legacy"] }
-tock-registers = "0.9"
+tock-registers = "0.10"
 memoffset = { version = ">=0.6.5", features = ["unstable_const"] }
 
-axerrno = "0.1.0"
+axerrno = "0.2"
 page_table_entry = "0.6"
 memory_addr = "0.4"
 
-axaddrspace = "0.1.4"
-axvcpu = "0.2"
-axvisor_api = "0.1"
+axaddrspace = "0.3"
+axvcpu = "0.3"
+axvisor_api = "0.3"

src/percpu.rs

@@ -12,10 +12,8 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-use core::marker::PhantomData;
-
 use axerrno::{AxError, AxResult};
-use axvcpu::{AxArchPerCpu, AxVCpuHal};
+use axvcpu::AxArchPerCpu;
 
 use riscv::register::sie;
 use riscv_h::register::{hedeleg, hideleg, hvip};
@@ -24,19 +22,15 @@ use crate::consts::traps;
 use crate::has_hardware_support;
 
 /// Risc-V per-CPU state.
-pub struct RISCVPerCpu<H: AxVCpuHal> {
-    _marker: PhantomData<H>,
-}
+pub struct RISCVPerCpu;
 
-impl<H: AxVCpuHal> AxArchPerCpu for RISCVPerCpu<H> {
+impl AxArchPerCpu for RISCVPerCpu {
     fn new(_cpu_id: usize) -> AxResult<Self> {
         unsafe {
             setup_csrs();
         }
 
-        Ok(Self {
-            _marker: PhantomData,
-        })
+        Ok(Self)
     }
 
     fn is_enabled(&self) -> bool {

src/vcpu.rs

@@ -36,8 +36,8 @@ use crate::{
 };
 
 use axaddrspace::{GuestPhysAddr, GuestVirtAddr, HostPhysAddr, MappingFlags, device::AccessWidth};
-use axerrno::{AxError::InvalidData, AxResult};
-use axvcpu::{AxVCpuExitReason, AxVCpuHal};
+use axerrno::{AxErrorKind::InvalidData, AxResult};
+use axvcpu::AxVCpuExitReason;
 
 unsafe extern "C" {
     fn _run_guest(state: *mut VmCpuRegisters);
@@ -57,10 +57,9 @@ pub struct VCpuConfig {}
 
 #[derive(Default)]
 /// A virtual CPU within a guest
-pub struct RISCVVCpu<H: AxVCpuHal> {
+pub struct RISCVVCpu {
     regs: VmCpuRegisters,
     sbi: RISCVVCpuSbi,
-    _marker: core::marker::PhantomData<H>,
 }
 
 #[derive(RustSBI)]
@@ -76,7 +75,7 @@ impl Default for RISCVVCpuSbi {
     }
 }
 
-impl<H: AxVCpuHal> axvcpu::AxArchVCpu for RISCVVCpu<H> {
+impl axvcpu::AxArchVCpu for RISCVVCpu {
     type CreateConfig = RISCVVCpuCreateConfig;
 
     type SetupConfig = ();
@@ -92,7 +91,6 @@ impl<H: AxVCpuHal> axvcpu::AxArchVCpu for RISCVVCpu<H> {
         Ok(Self {
             regs,
             sbi: RISCVVCpuSbi::default(),
-            _marker: core::marker::PhantomData,
         })
     }
 
@@ -228,7 +226,7 @@ impl<H: AxVCpuHal> axvcpu::AxArchVCpu for RISCVVCpu<H> {
     }
 }
 
-impl<H: AxVCpuHal> RISCVVCpu<H> {
+impl RISCVVCpu {
     /// Gets one of the vCPU's general purpose registers.
     pub fn get_gpr(&self, index: GprIndex) -> usize {
         self.regs.guest_regs.gprs.reg(index)
@@ -250,7 +248,7 @@ impl<H: AxVCpuHal> RISCVVCpu<H> {
     }
 }
 
-impl<H: AxVCpuHal> RISCVVCpu<H> {
+impl RISCVVCpu {
     fn vmexit_handler(&mut self) -> AxResult<AxVCpuExitReason> {
         self.regs.trap_csrs.load_from_hw();