[feat] Add hypervisor support for aarch64

[numpy1314]

update aarch64 hv part

[equation314]

It is a duplicate of #7 which was nearly approved the review, but for some reason it got closed.

[numpy1314]

It is a duplicate of #7 which was nearly approved the review, but for some reason it got closed.

Yes, that person is busy now, so I take over this part of the work.

[equation314]

Please refer to the review comments of #7.

[numpy1314]

Please refer to the review comments of #7.

Modification has been completed，and I wonder if it is necessary to remove the inner shared suffix in the assembly code section on line 146

[equation314]

The operand should be bits 12..55 of virtual address, see the official doccument and arceos-org/page_table_multiarch#21.

[equation314]

Modification has been completed，and I wonder if it is necessary to remove the inner shared suffix in the assembly code section on line 146

The inner share suffix means broadcast to all cores in the same shared domain.

When we flush the TlB by address, it is often the case that one core modifies the page table mapping, which needs to take effect on other cores as well, so there is an is suffix.

When we flush all tlb entries, it is often during the initialization phase, when all cores will execute this operation to flush their own local TLBs, so there is no need for the is suffix.

Linux also use use is suffix to flush the TLB by virtual address ranges: https://github.com/torvalds/linux/blob/dfba48a70cb68888efb494c9642502efe73614ed/arch/arm64/include/asm/tlbflush.h#L470

[numpy1314]

Modification has been completed，and I wonder if it is necessary to remove the inner shared suffix in the assembly code section on line 146

The inner share suffix means broadcast to all cores in the same shared domain.

When we flush the TlB by address, it is often the case that one core modifies the page table mapping, which needs to take effect on other cores as well, so there is an is suffix.

When we flush all tlb entries, it is often during the initialization phase, when all cores will execute this operation to flush their own local TLBs, so there is no need for the is suffix.

Linux also use use is suffix to flush the TLB by virtual address ranges: https://github.com/torvalds/linux/blob/dfba48a70cb68888efb494c9642502efe73614ed/arch/arm64/include/asm/tlbflush.h#L470

Thank you very much. I ignored the processing of high bits before. I also learned the specific mechanism of refreshing specific addresses and refreshing the entire page table in multi-core situations. Here I want to confirm whether my understanding is correct: when we modify the mapping of a specific address, this operation will affect the TLB of all cores in the shared domain, but when the full TLB is refreshed, each core executes it independently, so there is no need to broadcast this instruction to other cores in the inner shared domain, right?

[equation314]

when we modify the mapping of a specific address, this operation will affect the TLB of all cores in the shared domain, but when the full TLB is refreshed, each core executes it independently, so there is no need to broadcast this instruction to other cores in the inner shared domain, right?

Yep

[equation314]

Remove meaningless comments

[numpy1314]

Thanks, useless comments have been removed