style: introduce rustfmt.toml

rustfmt.toml

@@ -0,0 +1,16 @@
+unstable_features = true
+
+style_edition = "2024"
+
+group_imports = "StdExternalCrate"
+imports_granularity = "Crate"
+
+normalize_comments = true
+
+condense_wildcard_suffixes = true
+enum_discrim_align_threshold = 20
+use_field_init_shorthand = true
+
+format_strings = true
+format_code_in_doc_comments = true
+format_macro_matchers = true

src/aarch64/context.rs

@@ -1,5 +1,5 @@
-use core::arch::naked_asm;
-use core::fmt;
+use core::{arch::naked_asm, fmt};
+
 use memory_addr::VirtAddr;
 
 /// Saved registers when a trap (exception) occurs.

src/aarch64/trap.rs

@@ -11,9 +11,9 @@ core::arch::global_asm!(include_str!("trap.S"));
 #[allow(dead_code)]
 enum TrapKind {
     Synchronous = 0,
-    Irq = 1,
-    Fiq = 2,
-    SError = 3,
+    Irq         = 1,
+    Fiq         = 2,
+    SError      = 3,
 }
 
 #[repr(u8)]

src/arm/asm.rs

@@ -1,11 +1,10 @@
 //! Wrapper functions for assembly instructions.
 
 use core::arch::asm;
-use memory_addr::{PhysAddr, VirtAddr};
-
-use aarch32_cpu::register::*;
 
 pub use aarch32_cpu::asm::{dmb, dsb, isb, sev, wfe, wfi};
+use aarch32_cpu::register::*;
+use memory_addr::{PhysAddr, VirtAddr};
 
 /// Allows the current CPU to respond to interrupts.
 #[inline]

src/arm/context.rs

@@ -1,5 +1,5 @@
-use core::arch::naked_asm;
-use core::fmt;
+use core::{arch::naked_asm, fmt};
+
 use memory_addr::VirtAddr;
 
 /// Saved registers when a trap (exception) occurs.

src/arm/init.rs

@@ -1,8 +1,9 @@
 //! Helper functions to initialize the CPU states on systems bootstrapping.
 
-use crate::asm;
 use memory_addr::PhysAddr;
 
+use crate::asm;
+
 /// Configures and enables the MMU on the current CPU.
 ///
 /// It first sets `TTBR0`, `TTBR1`, `TTBCR` registers to the conventional values,

src/arm/trap.rs

@@ -17,21 +17,21 @@ core::arch::global_asm!(include_str!("trap.S"));
 #[allow(dead_code)]
 pub enum TrapKind {
     /// Reset exception
-    Reset = 0,
+    Reset         = 0,
     /// Undefined instruction exception
-    Undefined = 1,
+    Undefined     = 1,
     /// Software interrupt (SVC) exception
-    Svc = 2,
+    Svc           = 2,
     /// Prefetch abort exception
     PrefetchAbort = 3,
     /// Data abort exception
-    DataAbort = 4,
+    DataAbort     = 4,
     /// Reserved (should never occur)
-    Reserved = 5,
+    Reserved      = 5,
     /// IRQ interrupt
-    Irq = 6,
+    Irq           = 6,
     /// FIQ interrupt
-    Fiq = 7,
+    Fiq           = 7,
 }
 
 /// Handler for invalid/unhandled exceptions.

src/loongarch64/context.rs

@@ -1,6 +1,7 @@
 use core::arch::naked_asm;
 #[cfg(feature = "fp-simd")]
 use core::mem::offset_of;
+
 use memory_addr::VirtAddr;
 
 /// General registers of Loongarch64.

src/riscv/asm.rs

@@ -1,8 +1,10 @@
 //! Wrapper functions for assembly instructions.
 
 use memory_addr::{PhysAddr, VirtAddr};
-use riscv::asm;
-use riscv::register::{satp, sstatus, stvec};
+use riscv::{
+    asm,
+    register::{satp, sstatus, stvec},
+};
 
 /// Allows the current CPU to respond to interrupts.
 #[inline]

src/riscv/context.rs

@@ -1,4 +1,5 @@
 use core::arch::naked_asm;
+
 use memory_addr::VirtAddr;
 use riscv::register::sstatus::{self, FS};
 
@@ -98,7 +99,7 @@ impl FpState {
         unsafe { sstatus::set_fs(next_fp_state.fs) };
         // restore the next task's FP state
         match next_fp_state.fs {
-            FS::Clean => next_fp_state.restore(), // the next task's FP state is clean, we should restore it
+            FS::Clean => next_fp_state.restore(), /* the next task's FP state is clean, we should restore it */
             FS::Initial => FpState::clear(),      // restore the FP state as constant values(all 0)
             FS::Off => {}                         // do nothing
             FS::Dirty => unreachable!("FP state of the next task should not be dirty"),

src/riscv/trap.rs

@@ -1,8 +1,12 @@
-use riscv::interrupt::supervisor::{Exception as E, Interrupt as I};
-use riscv::interrupt::Trap;
 #[cfg(feature = "fp-simd")]
 use riscv::register::sstatus;
-use riscv::register::{scause, stval};
+use riscv::{
+    interrupt::{
+        Trap,
+        supervisor::{Exception as E, Interrupt as I},
+    },
+    register::{scause, stval},
+};
 
 use super::TrapFrame;
 use crate::trap::PageFaultFlags;

src/riscv/uspace.rs

@@ -1,9 +1,9 @@
 //! Structures and functions for user space.
 
 use memory_addr::VirtAddr;
-use riscv::register::sstatus::Sstatus;
 #[cfg(feature = "fp-simd")]
 use riscv::register::sstatus::FS;
+use riscv::register::sstatus::Sstatus;
 
 use crate::{GeneralRegisters, TrapFrame};
 
@@ -23,9 +23,7 @@ impl UspaceContext {
         sstatus.set_spie(true); // enable interrupts
         sstatus.set_sum(true); // enable user memory access in supervisor mode
         #[cfg(feature = "fp-simd")]
-        {
-            sstatus.set_fs(FS::Initial); // set the FPU to initial state
-        }
+        sstatus.set_fs(FS::Initial); // set the FPU to initial state
 
         Self(TrapFrame {
             regs: GeneralRegisters {

src/trap.rs

@@ -1,11 +1,12 @@
 //! Trap handling.
 
+pub use linkme::{
+    distributed_slice as def_trap_handler, distributed_slice as register_trap_handler,
+};
 use memory_addr::VirtAddr;
+pub use page_table_entry::MappingFlags as PageFaultFlags;
 
 pub use crate::TrapFrame;
-pub use linkme::distributed_slice as def_trap_handler;
-pub use linkme::distributed_slice as register_trap_handler;
-pub use page_table_entry::MappingFlags as PageFaultFlags;
 
 /// A slice of IRQ handler functions.
 #[def_trap_handler]

src/x86_64/context.rs

@@ -1,4 +1,5 @@
 use core::{arch::naked_asm, fmt};
+
 use memory_addr::VirtAddr;
 
 /// Saved registers when a trap (interrupt or exception) occurs.

src/x86_64/gdt.rs

@@ -1,11 +1,17 @@
 use core::fmt;
 
 use lazyinit::LazyInit;
-use x86_64::instructions::tables::{lgdt, load_tss};
-use x86_64::registers::segmentation::{Segment, SegmentSelector, CS};
-use x86_64::structures::gdt::{Descriptor, DescriptorFlags};
-use x86_64::structures::{tss::TaskStateSegment, DescriptorTablePointer};
-use x86_64::{addr::VirtAddr, PrivilegeLevel};
+use x86_64::{
+    PrivilegeLevel,
+    addr::VirtAddr,
+    instructions::tables::{lgdt, load_tss},
+    registers::segmentation::{CS, Segment, SegmentSelector},
+    structures::{
+        DescriptorTablePointer,
+        gdt::{Descriptor, DescriptorFlags},
+        tss::TaskStateSegment,
+    },
+};
 
 #[unsafe(no_mangle)]
 #[percpu::def_percpu]

src/x86_64/idt.rs

@@ -1,9 +1,13 @@
 use core::fmt;
 
 use lazyinit::LazyInit;
-use x86_64::addr::VirtAddr;
-use x86_64::structures::idt::{Entry, HandlerFunc, InterruptDescriptorTable};
-use x86_64::structures::DescriptorTablePointer;
+use x86_64::{
+    addr::VirtAddr,
+    structures::{
+        DescriptorTablePointer,
+        idt::{Entry, HandlerFunc, InterruptDescriptorTable},
+    },
+};
 
 const NUM_INT: usize = 256;
 

src/x86_64/init.rs

@@ -1,10 +1,8 @@
 //! Helper functions to initialize the CPU states on systems bootstrapping.
 
-pub use super::gdt::init_gdt;
-pub use super::idt::init_idt;
-
 #[cfg(feature = "uspace")]
 pub use super::syscall::init_syscall;
+pub use super::{gdt::init_gdt, idt::init_idt};
 
 /// Initializes the per-CPU data structures.
 ///

src/x86_64/mod.rs

@@ -14,7 +14,10 @@ mod syscall;
 #[cfg(feature = "uspace")]
 pub mod uspace;
 
-pub use self::context::{ExtendedState, FxsaveArea, TaskContext, TrapFrame};
-pub use self::gdt::GdtStruct;
-pub use self::idt::IdtStruct;
 pub use x86_64::structures::tss::TaskStateSegment;
+
+pub use self::{
+    context::{ExtendedState, FxsaveArea, TaskContext, TrapFrame},
+    gdt::GdtStruct,
+    idt::IdtStruct,
+};

src/x86_64/syscall.rs

@@ -1,7 +1,11 @@
-use x86_64::addr::VirtAddr;
-use x86_64::registers::model_specific::{Efer, EferFlags, KernelGsBase, LStar, SFMask, Star};
-use x86_64::registers::rflags::RFlags;
-use x86_64::structures::tss::TaskStateSegment;
+use x86_64::{
+    addr::VirtAddr,
+    registers::{
+        model_specific::{Efer, EferFlags, KernelGsBase, LStar, SFMask, Star},
+        rflags::RFlags,
+    },
+    structures::tss::TaskStateSegment,
+};
 
 use super::{GdtStruct, TrapFrame};
 

src/x86_64/uspace.rs

@@ -16,8 +16,9 @@ impl UspaceContext {
     /// Creates a new context with the given entry point, user stack pointer,
     /// and the argument.
     pub fn new(entry: usize, ustack_top: VirtAddr, arg0: usize) -> Self {
-        use crate::GdtStruct;
         use x86_64::registers::rflags::RFlags;
+
+        use crate::GdtStruct;
         Self(TrapFrame {
             rdi: arg0 as _,
             rip: entry as _,