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fix(aarch64): TLB flush VA bits #21

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Merged
equation314 merged 1 commit into from
Jun 25, 2025
Merged

fix(aarch64): TLB flush VA bits #21

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3 changes: 2 additions & 1 deletion page_table_multiarch/src/arch/aarch64.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,8 @@ impl PagingMetaData for A64PagingMetaData {
unsafe {
if let Some(vaddr) = vaddr {
// TLB Invalidate by VA, All ASID, EL1, Inner Shareable
asm!("tlbi vaae1is, {}; dsb sy; isb", in(reg) vaddr.as_usize())
const VA_MASK: usize = (1 << 44) - 1; // VA[55:12] => bits[43:0]
asm!("tlbi vaae1is, {}; dsb sy; isb", in(reg) ((vaddr.as_usize() >> 12) & VA_MASK))
} else {
// TLB Invalidate by VMID, All at stage 1, EL1
asm!("tlbi vmalle1; dsb sy; isb")
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